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Required Senior HW architect
About the group:
We are a highly experienced architecture group specializing in switch processing, with deep expertise in both hardware and software architecture in the high-speed networking domain.
Our innovative packet processors power some of the most advanced data centers in the world and are designed into tier-1 vendor platforms. With state-of-the-art technology, a strong track record of industry recognition, and multiple award-winning achievements, we continuously push the boundaries of performance and scalability.
Our group is involved across the entire development lifecycle - from early research and architectural definition to silicon production - working on both research initiatives and production-grade products.
What will you be doing?
Lead research, evaluation, and architectural definition of next-generation chips - from requirements through production.
Define next-generation Packet Processor / Datapath / Congestion Management architectures for high-performance, complex SoC Ethernet Switches.
Design the system architecture and detailed micro-architecture definition across major functional blocks.
Collaborate closely with design, verification, and modeling teams to ensure architectural intent is fully realized.
Work cross-functionally with other architecture teams to shape cohesive system solutions.
Explore and evaluate new technologies and innovative approaches for future products.

Required CPU Core Micro Architect
Job Description
Our goal is to design cutting-edge CPUs for smartphones, servers, and desktops, and we need the very best talent to help us achieve it!
The CPU Micro architect will take charge in defining a processor Micro architecture features that will improve the performance and reduce the power consumption of the CPU core. This architect will use a performance simulator to explore his ideas and will analyze implementability of these features: Power, Timing, Area. This architect will utilize his processor and VLSI design experience to develop many advanced features for Huawei processors.

Required Wafer-Scale System: Computation (LLM) and Communication (NoC) Co-Design
In this job opening, we are seeking a highly motivated and visionary researcher to join our team focused on chiplet-based computing systems. This role involves research and development in chiplet-based architectures, aiming to overcome performance and scalability limits of traditional compute platforms.
Responsibilities:
Conduct cutting-edge research on the co-design of communication and computation for wafer-scale systems. On the communication side, the work focuses on architecting Networks-on-Chip, providing scalable, high-bandwidth, and ultra-low-latency interconnects that efficiently span multiple dies and support fine-grained data movement. On the computation side, the research emphasizes optimizing and mapping training and inference workloads to fully exploit wafer-scale resources, improving performance, scalability, and energy efficiency through intelligent task placement and scheduling.
Investigate various aspects of system design, including:
Network-on-Chip design, further including Topology exploration, routing algorithms, and protocol/flow-control design to support high-throughput collective communication, low-latency synchronization, and efficient model/data parallelism
Expressing and Mapping LLM Parallelism to Wafer-Scale System that simplify LLM parallelism (e.g., tensor, pipeline, and data parallelism) and efficiently map training and inference workloads onto wafer-scale system.

We are looking for a highly analytical, detail-oriented Innovation Expert to join our Open Innovation team. This role is ideal for candidates who sit at the intersection of deep tech, startup ecosystem and academy, possessing strong technology analytical skills, clear communication, and a foundational background in computer architecture research.
In this role, you will drive our external innovation strategy by managing academic research collaborations, scouting early-stage deep-tech startups and conducting technical due diligence.
Key Responsibilities:
Academic Cooperation & Research Partnerships: Identify and build direct collaboration agreements with world-class professors, research labs, and universities. Facilitate joint research projects, tech-transfer initiatives, and track academic spin-offs.
Startup Scouting & Ecosystem Mapping: Actively identify, source, and map early-stage deep-tech startups and emerging tech companies globally within the companys strategic domains.
Technical Due Diligence: Evaluate startup technologies, product-market fit, and team capabilities. Analyze technical validity and assess how external innovations align with our internal roadmaps.
Ecosystem Analysis: Conduct deep-dive analyses of startup ecosystems, venture capital trends, and academic spin-offs to identify high-potential investment and collaboration opportunities.
Investment & Collaboration Support: Synthesize technical and commercial findings into clear, structured scouting reports, investment tech memos, and presentations for senior leadership to drive partnership or investment decisions.
Cross-Border Collaboration: Act as a bridge between startup founders, academic innovators, and internal global teams (including European and China-based business units) to facilitate joint POCs, or investment reviews.
Track Tech Domains: AI infrastructure, advanced semiconductors, hardware-software co-design, and AI data movement.

Semi Conductor Devices (SCD), a leading worldwide supplier of high-end Infrared Detectors and thermal imaging cores, is looking for an Analog / Mixed-Signal VLSI Designer to join its VLSI R&D group. The role involves design and validation of custom analog and mixed-signal ASICs (ROICs) for advanced IR imaging systems, working closely with experienced analog, digital, system, and hardware teams.
Responsibilities:
Design and verify Analog and Mixed-Signal circuit blocks for IR image sensors (ROICs) under the guidance of senior designers Participate in the full ASIC development flow: specification review circuit design verification integration silicon bring-up lab validation Contribute to block-level simulations, documentation, and design reviews Work closely with digital designers, layout engineers, electronics, and system teams to support chip integration Support post-silicon validation and lab measurements, including debug and correlation to simulations Gain exposure to advanced CMOS processes, image sensor architectures, and system -driven design constraints.

Semi Conductor Devices (SCD), a worldwide leader of high-end Infrared Detectors and thermal video cores, is seeking a Senior Digital VLSI Engineer to participate in the definition, design, verification, implementation, and silicon validation of next-generation infrared image sensors. Responsibilities • Be part of a team defining future Image Sensor Digital controller Architecture • Participate in the digital design and verification effort of state-of-the-art IR Image Sensors, working closely with the Analog designers and Board designers (internal and external interfaces) • Take part in ASIC development lifecycle (pre- and post-silicon) – from Spec definition to block-level design, full-Chip till Silicon Validation in the laboratory and customer support • Lead the design and integration of complex digital blocks from specification to silicon • Drive VLSI innovation and integration of new technologies into projects and activities in the design organization

The Production TEST Engineer will develop and maintain TEST processes and TEST systems for BATM's products, at both card and system level. The role includes defining TEST plans for new products, building new TEST solutions and testers, and supporting the manufacturing floor through hands-on testing, debugging, and root-cause analysis- working closely with R&D, PLM, and Manufacturing. Responsibilities Define TEST plans and processes for new products (NPI). Develop new testers and testing solutions; maintain existing testers at card and system level. Perform hands-on testing, debugging and analysis of TEST results; identify issues and track root causes. TEST and support Optical Transceivers. Document technical TEST issues, solutions, and TEST procedures (ATP). Use AI-based tools to speed up TEST script development, automate log/ data analysis, and generate technical documentation.

Are you passionate about technology, customer engagement, and driving business growth? Join our team as a Strategic Account Manager and play a key role in expanding our presence within the Defense, Aerospace, Medical, and Industrial markets.
As the primary commercial interface for key customers, you will be responsible for developing strategic partnerships, identifying new opportunities, and managing complex sales cycles from initial engagement through successful business award.