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our company has been transforming computer graphics, pc gaming, and accelerated computing for more than 25 years. its a unique legacy of innovation thats fueled by great technology-and amazing people. today, were tapping into the unlimited potential of ai to define the next era of computing. an era in which our gpu acts as the brains of computers, robots, and self-driving cars that can understand the world. doing whats never been done before takes vision, innovation, and the worlds best talent. as an employee, youll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. come join the team and see how you can make a lasting impact on the world.
join our company, a world leader in computing technology and ai, where we are exploring new possibilities! our advanced development Network Engineer role in israel offers a special chance to contribute to large-scale network simulations for innovative ai datacenter research and development. you will be part of a dynamic team that values creativity and collaboration. if you are enthusiastic about technology and eager to build a significant difference, this is the place for you!
what you'll be doing:
developing a brand new digital twin powered by cuda technology for advanced research on data centers.
collaborating with a team of extraordinary engineers and researchers to develop and implement innovative solutions.
partnering with diverse teams to ensure smooth integration and deployment of network solutions.
continuously exploring new technologies and methodologies to improve our network capabilities.

we are seeking a highly motivated  system  architect to join our team of experts and help shape the future of ai & cloud computing. our next-generation bluefield dpus and connectx nics will be at the forefront of connecting and powering the world's most advanced compute clusters, from supercomputers used in ai research to cloud & Storage servers.
what you'll be doing:
define server platform architecture for next generation data center products for ai and cloud, focusing on dense networking solution.
design is highly restricted in space, power and thermals.
define board level and system management architectures for the different platforms
define board level integration and system model for reset, recovery and boot
partner with product, software, design and platform engineering groups for converging plans according to requirements
work with the software team on software and hardware apis
research next generation needs

we are looking for an experienced engineer with a strong background in asic design to join our chip design methodologies team based in tel aviv and yokneam. this team is responsible for establishing asic design methodologies, developing shared code, providing design guidance, and driving the adoption of new technologies. it plays a key role in ensuring chip design teams operate efficiently and adhere to best practices. this role offers an exciting opportunity to think innovatively and make a significant impact within a dynamic, technology-focused organization.
what you'll be doing:
develop ground-breaking methodologies and innovations to create flawless experience in chip design development
utilize, develop and assimilate ai-based tools and flows
collaborate with chip design stakeholders and peers across the teams to understand existing problems and form the best solutions and methodologies
get in touch with eda vendors to learn about cutting-edge tools/technology and apply them into our development process
develop training sessions and guide designers with best design practices
develop shared design code and solutions to be widely used by the chip design team

we are looking for a senior firmware Verification engineer to define, develop and maintain verification for our ethernet switches. this role offers you an excellent opportunity to participate in the development process of switches and gain a deep understanding in hardware, firmware and software systems in a rapidly growing field.
what youll be doing:
closely work with sdk/fw r&d architecture and QA to define, write and implement TEST plan for out product existing new features.
be responsible for verification and delivering different networking features.
define, develop and maintain verification procedure and reference model infrastructure - make TEST suites robust.
work with continuous integration system, regression tools, automate builds, run TEST suites and analyzing results
we are an equal opportunity employer and value diversity at our company. we do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.

we are looking for a dedicated SOC clocks design automation engineer to join our networking silicon team. in this role, youll focus on developing and supporting clock-related design flows and methodologies for SOC and networking chips, ensuring efficient and high-quality design implementation. youll also chip in to SOC top-level automation and integration activities, building on existing flow infrastructure to improve efficiency and consistency across projects. introduction
what you'll be doing:
develop and maintain design automation and methodologies for SOC and networking clock flows.
collaborate with design, sta, and project teams to ensure timely and high-quality design closure.
develop and improve SOC top-level automation scripts and flows built upon existing infrastructure and tools.
support SOC integration and construction flow activities across multiple projects.
assist in timing, power, and noise analysis to ensure efficient performance.

we are now looking for a formal verification manager to join our networking team!
as a formal verification manager in networking business unit, you will lead a team of highly skilled formal engineers responsible for verifying the next generation of cutting-edge network products and gpu technologies.
this is a unique opportunity to make a real impact at the heart of ai and hpc revolution, while working in a fast-paced, innovative environment.
you will be part of a passionate and experienced team using leading formal verification tools and methodologies to ensure design correctness at the highest level. your work will influence key architectural decisions and help deliver world-class silicon solutions for data centers, high-performance computing, networking, and Storage applications.
what youll be doing:
lead and grow a team of formal Verification engineers focused on pre-silicon formal verification of complex digital designs.
define and drive formal verification strategies and methodologies to prove the correctness of designs across multiple projects.
collaborate closely with architecture, design, dv teams to identify verification needs and drive closure.
provide technical guidance, mentoring, and support to engineers in the team.
own the planning and execution of formal verification deliverables to ensure high quality and timely tapeouts.

we are looking for best-in-class physical design power engineer to join our outstanding networking silicon power engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput, lowest latency and best power! come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
what you will be doing:
power optimization of physical design, of blocks/top-level/fc under challenging constraints.
optimization involves all aspects of physical design chip development (rtl2gds) - synthesis, power and clock distribution, place and route, timing closure, power and noise fixes.
power estimation and power modeling.

we are hiring a skilled senior dpu performance Validation engineer for our dpu product lines. this includes chip architecture performance characterization, debug, and validation across single-die and multi-die systems. working in the network silicon engineering group, you will be responsible for debugging, analyzing, and validating performance and functional behavior of current and future silicon devices. you will collaborate with chip design, verification, fw, and architecture teams to ensure successful product development with bold product cycles. the qualified candidate should be comfortable working in simulation and emulation environments, with strong skills in rtl-level debug, waveform analysis, and system -level performance root cause analysis.
what you will be doing:
learn and analyze system -level operation of dpus
debug and root-cause performance issues in pre-silicon environments, across rtl, waveform traces, and multi-die system simulations.
collaborate closely with design, verification, architecture, and performance modeling teams to isolate and fix issues.
develop and improve validation methodologies for performance experiments and data collection.
automate repetitive debug and validation tasks to scale coverage and efficiency.

ethernet switch firmware team is looking for a hardworking firmware manager to take part in leading and developing the firmware / hw interface in the next generation state of the art switch products.
as a member of our fw ethernet team, you will be responsible on a team of firmware engineers. it is expected that you will manage and guide the team for critical items.
this role offers you an excellent opportunity to accomplish something new, enabling understanding of hw and sw in a rapidly growing field while solving interesting technical issues and providing feedback to the hw team to improve the next asic generation.
what you will be doing:
lead a team of engineers and provide technical guidance to the team of highly skilled engineers. empower the team members to excel and increase team productivity.
lead the design and implementation of new features in the core of switch networking firmware.
drive and facilitate the planning, scheduling, and execution of the project and activities of the team
collaborate with architecture and different software design teams as part of the software development lifecycle.
work in pre and post-silicon development environments of next-generation switch networking products.
gain a deep understanding of networking technology, system debugging, and stacks, as well as the hw/fw/sw relationship.
innovate! bring networking products to shine in customers view

we are seeking a dedicated firmware engineer to join our nic firmware core team in beer-sheva/tel-aviv. you will contribute to the development of brand-new networking adapter technologies, elevating the performance of current and future our company devices. our company develops innovative and next-generation networking devices that are known for their outstanding performance and power efficiency. the position involves all aspects of firmware development, including design, micro-architecture, software interfaces, and verification. we are seeking a dedicated and motivated engineer who will contribute to the development of advanced technology network adapters. you will also have the opportunity to create features for leading cloud computing providers and high-performance computing networks.
what youll be doing:
take a part in the design, development, TEST, debug, and optimization of low-level firmware layer on next-generation network adapters up to package release
analyze, integrate, support, and debug low-level firmware layer on verification environments
collaborate with firmware, software, and architecture teams to analyze, design, and debug legacy and new low-level firmware flow
improve our team processes including design and implementation of new methodologies, automated processes.

we are looking for best-in-class physical design engineers to join our outstanding networking silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
what you'll be doing:
perform advanced static timing analysis (sta) for hsio at chiplet and fc level.
running prime time, review and debug timing paths, understand constraints, sdc generation, timing ecos generation.
identify convergence risks and work closely with physical design, rtl and dft teams, ensuring convergence throughout various project stages.
responsible for a full timing closer and quality approval from pre-layout sta model through signoff.
ai use for timing optimization and data analysis.

we are looking for best-in-class chip design engineers to join our outstanding networking silicon engineering team, developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! come and take a significant part in designing and verifying our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a huge impact in a technology-focused company.
what you will be doing:
join beer-sheva/tel-aviv group, working on design in the field of encryption accelerators.
design of chip blocks/entities according to specifications under challenging constraints and with high orientation to power, area and performance.
daily work will involve design and might involve any or all aspects of chip development including design and micro-architecture.
work closely with firmware and other groups around the globe.
work mode: hybrid home-office

we are looking for best-in-class physical design engineers to join our outstanding networking silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
what you'll be doing:
physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.
be exposed and work on a variety of exciting designs. resolving complex timing and congestion problems.
daily work involves all aspects of physical design chip development (rtl2gds) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
taking part in flow development.

are you passionate about working on a team that is at the cutting and bleeding edge of hardware technology? our design-for- TEST engineering team works on groundbreaking innovations involving crafting creative solutions for dft architecture, verification and post-silicon validation on some of the industry's most sophisticated semiconductor chips. we are looking for a dft engineer to join the atpg team. the position includes taking part in development of the next generation dft technologies and working closely with a wide range of our groups and aspects - chip design, backend, verification, and production testing.
working on the most advanced technologies and complex products, our dft solution are unique and innovative internal developments, and we are continuously improving and evolving the solution to meet the challenging goals. if you find groundbreaking technologies, and next generation products interesting, then this is the team for you. take opportunity to join our team for an exciting and educational environment, where every individual has significant contribution to our products and achievements!

we are looking for best-in-class chip design engineers to join our outstanding networking silicon engineering team, developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! come and take a significant part in designing and verifying our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a huge impact in a technology-focused company.
what you will be doing:
join tel-aviv/beer-sheva group, working on verification in the field of encryption accelerators.
verification of chip blocks/entities according to specifications under challenging constraints and with high orientation to power, area and performance.
daily work will involve verification and might involve any or all aspects of chip development including micro-architecture.
work closely with firmware and other groups around the globe.
work mode: hybrid home-office.