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be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
as a design team manager within the server chip design team, you will use your asic design experience to be part of a team that creates the SOC vlsi design cycle from start to finish. you will collaborate closely with design and Verification engineers in active projects, creating architecture definitions with rtl coding, and running block level simulations.in this role, you will oversee the intellectual property (ip) and SOC vlsi design cycle from architecture to production. you will own and manage ip, subsystems and SOC development, leading a group of designers and design tech leads. you will be responsible for mentoring and developing team members and tech leads, driving improvements in leadership, technical execution, and design flows.the ai and infrastructure team is redefining whats possible. we empower our customers with breakthrough capabilities and insights by delivering ai and infrastructure at unparalleled scale, efficiency, reliability and velocity. our customers include , cloud customers, and billions of our users worldwide. we're the driving team behind our groundbreaking innovations, empowering the development of our cutting-edge ai models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. from software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our tpus, vertex ai for our cloud, global networking, data center operations, systems research, and much more.
responsibilities
manage a team of tech leads and designers. develop and mentor team members, and communicate and co-work with multi-disciplined and multi-site teams.
lead design activities at ips, subsystems, and system -on-chips (socs).
plan, execute, track progress, assure quality, and report status of the assigned activity.
work closely with internal customers and support multiple activities and deliverables.
assure and manage deliverables quality at all rtl design categories including reviews, static checks, design for physical design, power, etc.

as a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. you develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of google users.
as a cmos technologist and foundry engineer, you'll be part of the growing chip design team. in this role, you'll be responsible for driving cmos (complementary metal oxide semiconductor) foundry partners, intellectual property (ip), and chip design and implementation teams to perform cmos transistor scaling and power/performance analysis (ppa), and producing technology roadmap benchmarks. you will also be involved in interfacing and driving our design ip partners.the ai and infrastructure team is redefining whats possible. we empower google customers with breakthrough capabilities and insights by delivering ai and infrastructure at unparalleled scale, efficiency, reliability and velocity. our customers include googlers, google cloud customers, and billions of google users worldwide. we're the driving force behind google's groundbreaking innovations, empowering the development of our cutting-edge ai models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. from software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our tpus, vertex ai for google cloud, google global networking, data center operations, systems research, and much more.
responsibilities
engage with cmos foundry partners, manage foundry design kits and design library collaterals, and work with our design teams to perform ppa simulations on benchmark circuits.
work with fab partners on device and circuit level TEST structures, TEST chips, and characterization and correlation of silicon data. you will use the results of this work to influence design optimizations.
work with ip partners, design, and physical design teams to design advanced cmos.
work with chip implementation and physical design teams on micro-architecture tradeoffs, support design tool flow bring-up, and address all physical implementation details leading to product tapeout.
work with our commercial and product teams on foundry and ip vendor management, track technology roadmaps, and determine appropriate technology and ip integration strategies.

be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
with your technical expertise you will manage project priorities, deadlines, and deliverables. you will design, develop, TEST, deploy, maintain, and enhance software solutions.the ml, systems, & cloud ai (msca) organization at our designs, implements, and manages the hardware, software, Machine Learning, and systems infrastructure for all our services (search, youtube, etc.) and our cloud. our end users are  cloud customers and the billions of people who use our services around the world. we prioritize security, efficiency, and reliability across everything we do - from developing our latest tpus to running a global network, while driving towards shaping the future of hyperscale computing. our global impact spans software and hardware, including our clouds vertex ai, the leading ai platform for bringing gemini models to enterprise customers.
responsibilities
create software solutions that improve the hardware post-silicon testing process through automation. this includes, but is not limited to, developing and maintaining an automatic TEST equipment (ate) program development infrastructure for both production and development environments.
propose, design and implement software automation that directly addresses bottlenecks in today's post-silicon TEST flow, from design for testing (dft) to ate.
review code developed by other developers and provide feedback to ensure best practices (e.g., style guidelines, checking code in, accuracy, testability, and efficiency).
contribute to existing documentation or educational content and adapt content based on product/program updates and user feedback.
triage product or system issues and debug/track/resolve by analyzing the sources of issues and the impact on hardware, network, or service operations and quality.

be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.as a power and signal integrity engineer, you will be responsible for the design and characterization of signal and power integrity of our ic designs. you will design the external electrical interfaces of the device, from their signal/power-integrity and electrical usage perspectives and set up methodologies, perform simulations, silicon characterization and correlations to ensure our ic designs meet systems design budgets and achieve the highest performance. you will work with systems architects, asic design, systems engineers, and partner cross-functionally with teams and external vendors/partners.the ml, systems, and cloud ai (msca) organization at our designs, implements, and manages the hardware, software, Machine Learning, and systems infrastructure for all our services (search, youtube, etc.) and our cloud. our end users are cloud customers and the billions of people who use our services around the world. we prioritize security, efficiency, and reliability across everything we do - from developing our latest tpus to running a global network, while driving towards shaping the future of hyperscale computing. our global impact spans software and hardware, including our clouds vertex ai, the leading ai platform for bringing gemini models to enterprise customers.
responsibilities
generate precise electrical models (e.g., s-parameters, spice models) for components such as packages, pcbs, and connectors for use in simulations.
simulate high speed interface electrical behavior using hspice or other circuit simulators.
execute lab measurements utilizing TEST equipment like oscilloscopes, vector network analyzers (vna), time domain reflectometers (tdr), spectrum analyzers to validate simulation outcomes and debug signal and power-related issues on silicon prototypes and boards.
establish design rules and guidelines for optimal signal/power integrity during pcb and package layout, ensuring high production yield and reliability.
document design specifications, analysis results, and validation reports to ensure compliance with standards and for future reference, while collaborating extensively with cross-functional teams, including asic architects, digital/analog designers, physical design/layout engineers, and system engineers

in this role, you will help build socs by driving quality and reliability processes from the integrated circuit (ic) perspective. working with various cross-functional teams, you will develop quality and reliability specifications, develop and deploy design guidelines, and develop and execute TEST plans. within the larger organization, you will collaborate with global hardware quality and reliability, silicon design, validation, and engineering teams. you will have an understanding of ic flows, wafer processing, testing, qualification, yield, reliability, and failure analysis.the ml, systems, & cloud ai (msca) organization at google designs, implements, and manages the hardware, software, Machine Learning, and systems infrastructure for all google services (search, youtube, etc.) and google cloud. our end users are googlers, cloud customers and the billions of people who use google services around the world. we prioritize security, efficiency, and reliability across everything we do - from developing our latest tpus to running a global network, while driving towards shaping the future of hyperscale computing. our global impact spans software and hardware, including google clouds vertex ai, the leading ai platform for bringing gemini models to enterprise customers.
responsibilities
define and lead qualification hardware and TEST developments in front of internal teams and external vendors.
define and execute silicon and package qualification activities (e.g., htol, elfr, esd/lu, b/hast, thb, etc.).
extract, manipulate, and analyze large volumes of data from silicon and package qualification programs (e.g., htol, elfr, esd, lu, uhast, tct, etc.), high volume mfg, and field returns to identify failure mechanisms, reliability trends, and opportunities for yield, quality, and reliability improvement.
own cross-functional investigation of ic quality and reliability issues to identify root causes and develop solutions (e.g., rma triage, analytics, failure analysis, etc.).
develop and implement physics-based statistical quality and reliability models (e.g., elf, tddb, nbti, hci, time zero failures, etc.) to predict silicon device failure mechanisms, degradation patterns, and lifetime behaviors.

about the job
be part of a team that pushes boundaries, developing custom silicon solutions that power the future of direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next-generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.the ml, systems, & cloud ai (msca) organization at google designs, implements, and manages the hardware, software, Machine Learning, and systems infrastructure for all google services (search, youtube, etc.) and google cloud. our end users are googlers, cloud customers and the billions of people who use google services around the world. we prioritize security, efficiency, and reliability across everything we do - from developing our latest tpus to running a global network, while driving towards shaping the future of hyperscale computing. our global impact spans software and hardware, including google clouds vertex ai, the leading ai platform for bringing gemini models to enterprise customers.
responsibilities
lead the schematic capture and component selection for high-density, multi-layer pcbs (20+ layers) incorporating high-power asics (tpus/cpus), fpgas, and high-speed memory (hbm/ddr5).
design and validate high-speed interfaces including pcie gen 6.0/7.0, 400g/800g/1.6t ethernet (pam4). collaborate with signal integrity (si) engineers to define routing constraints and stack-up.
design multi-phase power regulators (vrms) capable of delivering >1000a currents with fast transient response for ai processors.
work with pcb layout designers to guide placement and routing of critical signals and power planes.
lead the lab bring-up of first-silicon/first-board by debugging hardware issues using oscilloscopes, tdrs, and logic analyzers to root-cause failures to component, assembly, or design issues.

we are a fast-growing, global leader in energy-based solutions for Aesthetics and Eye-Care. We are based in Yokneam, Israel (with offices also in Tel-Aviv) with a strong business performance worldwide.
we are looking for an Electronic Engineer to join the Engineering Department."
Job Description
Redesign electronic boards to improve quality and replace obsolete parts.
Find and approve alternatives to obsolete or long lead time parts.
Define and perform validation and verification tests.
Define test procedures for electronic boards.
Support production lines by failures investigation and problems solving.

Managing a service product throughout its entire life cycle. This involves creating comprehensive technical documents and training programs, as well as facilitating communication between internal departments to ensure accurate execution of product services and processes. The role also focuses on ensuring the profitability and market success of the service, requiring collaboration with various organizational groups and proactive problem-solving to preempt potential issues and provide effective solutions.
Provide support to company subsidiaries, service department, distributors, and service recondition center
Prepare technical documentation: product descriptions, service manuals, spare parts lists, technical Notes and training programs
Manage and analyze the product service activity from profit and loss aspects, and ensures management of a profitable service in the marketplace
Develops pricing and pricing changes and manages tariff updates in partnership with After-Sale and Finance.
Interfaces between the field and various organizational groups like Engineering, R&D, Planning, Financial Controls/Management Accounting, Sales, Marketing, etc.
Leads regularly scheduled meetings focused on system and operational solutions for failures, product changes, and new product development.
Implement and integrate new products and new processes with service field teams and subsidiaries
Define service processes, spare parts, tools, and testing criteria
Training-lead frontal classroom training courses including theory and hands-on sessions
Track faults and malfunctions, perform technical investigations, and apply conclusions
Execute global service and control policy and maintain compliance with company policies and procedures.

abra professional services is seeking for an Field Technician We are looking for a Field Technician – Certified Electrician to join the Operations team and support the maintenance and operation of cellular network infrastructure in the Northern region. The role involves extensive field work, including configuration, maintenance, and troubleshooting of cellular sites, radio equipment, and transmission systems. The technician will be responsible for ensuring network availability, performance, and quality while working in dynamic and sometimes challenging environmental conditions. Key Responsibilities:
* Maintenance and operation of cellular network infrastructure
* Configuration and commissioning of cellular sites, including radio and transmission equipment
* Troubleshooting and resolving faults at cellular sites
* Integration of cellular sites, including RF chains, antennas, radio systems, and transmission equipment
* Installation, operation, and maintenance of AC/DC power systems
* Field work under varying environmental conditions
* Participation in on-call rotations, including nights, weekends, and holidays

We are looking for a Verification Team Leader for our team in Haifa to drive verification for next-generation PHY IPs . The PHY DV team operates at the intersection of verification, research, and innovation, continuously improving techniques, models, and flows to increase the efficiency and quality of PHY verification. This is a hands-on technical leadership role, combining deep verification expertise with team leadership and close collaboration with design, architecture, firmware, and system teams.
Description
Lead the verification team, including hiring, planning, and communication with management.
Strong teamwork and communication skills.
Responsibilities
Lead the verification team, including hiring, planning, and communication with management.
Define verification architecture and lead for execution
Own verification methodologies, standards, and best practices across the team

We are looking for a hands-on, experienced Physical Design Engineer to join us and help define and implement next-generation AI SoC in an advanced technology node

You will play a key role in building and leading our physical design team, developing flows and methodologies, and driving the full RTL-to-GDSII implementation and signoff for one of the most advanced SoCs in the industry.
What Youll Do

Take part in shaping methodology and best practices in advanced technologies

Drive end-to-end implementation: synthesis, P&R, timing closure, and signoff

Collaborate closely with architecture and design teams on timing, floorplaning, partitioning, and power specification

Define and optimize static timing constraints, area, and power goals at block and top levels

Take part in flow development and automation to improve efficiency and quality of results

looking for a senior VLSI Design Engineer highly experienced in developing designs for complex SoC devices, from arch/uarch definition to coding and verification. In this position you will have end-to-end responsibility for all design flow. In this position you will be responsible for full cluster/block uarch, design, initial synth, lint, integrating and supporting PD, DFT and verification.

If you are curious, innovative, have strong technical skills with a hands-on approach, and understand the full design, system view and SW integration requirements, this position is for you!