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which department will you join?
our hw team - a group designing the eyeq chips for adas and autonomous cars. the group is responsible for all disciplines of development, including but not limited to logic design, design verification, microarchitecture, analog and circuit design and layout, physical and structural design ( backend ), product and TEST engineering.
each physical design engineer has an end to end responsibility from definition, execution & full signoffs, working closely with design & architecture teams for constraints development, design review & rtl modifications to achieve converges were looking for a physical design engineer to join the growing physical design team, responsible for state of the art SOC design from definition to tape-out. what will your job look like:
hands-on physical design block owner from rtl to gds.
floorplan exploration with guidance and collaboration with Front-End and architecture teams.
sta: work with fe and floor planner to manage block and top level constraints and 1st level of timing analysis.
synthesis exploration and final synthesis netlist: scan insertion @ synthesis, clean checks from lint, upf & spyglass.
place & route: from synthesis netlist to final layout and signoff verification with target to achieve best power performance and area.

which department will you join?
epg is a fast-paced, dynamic, and startup-like group responsible for researching, incubating and developing next-generation technologies and ideas, with a strong orientation towards computer vision, Machine Learning, data, and ai.
the group hosts a diverse team of scientists, engineers and developers to research, realize, and bring to market innovative new products, leveraging cutting-edge technologies, skills and capabilities.
were looking for a backend expert to join the growing physical design team, responsible for state of the art SOC design from definition to tape-out.
what will your job look like:
hands-on physical design block owner from rtl to gds.
floorplan exploration with guidance and collaboration with Front-End and architecture teams.
sta: work with fe and floor planner to manage block and top level constraints and 1st level of timing analysis.
synthesis exploration and final synthesis netlist: scan insertion @ synthesis, clean checks from lint, upf & spyglass.
place & route: from synthesis netlist to final layout and signoff verification with target to achieve best power performance and area.

we are seeking a highly motivated system Software manager to lead a team driving the development of next-generation communication software and products, building on our industry-leading nvlink and nvswitch technologies. this role combines technical leadership with hands-on development activities, driving innovation at the core ofdata center ecosystem.
what you will be doing:
lead, mentor, and grow your engineering team while overseeing project planning, execution, and ensuring the quality and performance of all deliverables.
own major features and drive the teams roadmap that aligns with ambitious goals and dynamic customer requirements.
grow the local team while collaborating with a wide range of cross-business unit teams both on-site and locally.
continuously evaluate and identify opportunities to improve processes, infrastructure, and practices to ensure efficient, transparent, and high-quality team execution.
this is a technical leadership role, with active involvement in feature design and implementation.

as a senior software engineer in the gpu networking architecture team, youll lead advanced development and poc efforts for ai infrastructure solutions. you'll be collaborating with experts across distributed ai, deep learning, networking os, virtualization, Storage, and more. come and join us for the cutting edge in gpu networking!
what youll be doing:
drive advanced development and pocs for ai infrastructure solutions in cutting-edge ai networks, integrating innovative software and hardware.
demonstrate team architectural concepts with larger nvidia ai software stacks.
work closely with various groups within nvidia to bring ai network technologies to reality, including gpu and switch hw and sw teams, product as well as fellow architects.

we are now looking for a chip design Verification engineer to join the chip design methodologies team. the team is in charge of the verification methodologies, shared code, training, and embracing new technologies. one of our main goals is to make sure that the team works in an efficient manner, and provides high-quality deliveries. this position offers the opportunity to have real impact in a dynamic, technology-focused company.
what you'll be doing:
develop shared verification code and solutions to be widely used by the chip design team.
develop groundbreaking methodologies to create a flawless experience for Verification engineers to keep the focus on new problems.
collaborate with the design automation team to provide end-to-end solutions that combine verification, simulation, and automation.
get in touch with eda vendors to learn about cutting-edge tools/technology and apply them into our verification process.
understand the design, define the verification scope, develop the verification infrastructure and verify the correctness of the design.
collaborate with designers, verification specialists to accomplish your tasks.
develop training sessions.

we are now looking for a chip design engineer to join our switch silicon team for verification / design roles. as a chip design engineer at our networking business unit, you'll join a group of passionate engineers to design, implement and verify the next generation state-of-the-art switch silicon chips. in this position, you'll make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!
what you'll be doing:
work in a combined design and verification team which develops some of the switch silicon core units.
micro-architecture for rtl and simulation environment planning for units and modules.
design/verify rtl units/blocks according to arch. specifications under challenging constraints with high orientation to power, area, and performance.
build reference models, verify, and simulate chip blocks/entities according to specifications.
rtl synthesis, timing, supporting verification, and silicon post to activities.
work closely with multiple teams within organizations such as architecture, full chip micro-architecture, be, and fw.

our company is hiring a senior, hands-on engineer to lead technical innovation in our design verification (dv) automation infrastructure. this role requires a strong design/verification background combined with a proactive approach - identifying inefficiencies, proposing creative solutions, and implementing them with high ownership and impact. you will directly influence how verification is performed across our next-generation networking chips, enabling more scalable, efficient, and robust flows for complex asics powering the ai revolution. 
what you'll be doing:
lead the development of advanced verification automation tools, regression flows, and debug infrastructure.
identify key challenges and inefficiencies in current dv methodologies and proactively propose and implement improvements.
work closely with dv engineers, design teams, and tool developers to ensure solutions are practical and impactful.
balance innovation with hands-on engagement in daily dv issues - keeping a strong connection to real-world challenges and support needs.
act as a technical leader within the team, driving discussions, mentoring peers, and crafting strategic directions for dv automation.

looking for firmware engineer to join a team that works on nvidia ethernet switch. you will take part as a fw micro architect in full-cycle firmware development for new and existing products using modern software development tools and approaches.
if you're creative, responsible, hardworking, and autonomous, we want to hear from you!
what you'll be doing:
closely work with sw & hw architecture and different software develop teams to define the fw architecture for new features/improvements.
identify & diagnose high-value data path performance issues.
aim for high quality thinking and creative ways to improve fw performance, scalability and working methodologies.
you will learn how a big software project is operated, maintained, qualified and released, and how hardware and firmware are developed.
collaborate with other nvidia r&d teams around the globe.

seeking a visionary ai Verification engineer to join our chip design methodologies team. were expanding how we use ai across all our verification methods. in this role, youll help us figure out where ai fits best and build the 'brains' behind our tools. youll help us leverage ai, utilizing llms and Machine Learning -to help us debug complex chips faster and more efficiently
what youll be doing
ai ecosystem development: build and deploy an ai verification environment, moving from manual testbenches to automated stimulus generation and coverage closure.
next-gen tooling: develop and integrate ai agents and ml models directly within the verification toolchain to automate intent-to-testbench workflows.
intelligent debugging: create and refine ai-based debug assistants that can analyze simulation failures, categorize bugs, and suggest fixes autonomously.
methodology innovation: research and apply groundbreaking ai approaches (such as reinforcement learning or llms) to address the "state-space explosion" in chip verification.
collaborative intelligence: work with design automation teams and eda vendors to ensure our ai solutions provide end-to-end efficiency from rtl to gds.
leadership & training: act as the authority, training the broader team on how to bring to bear ai tools and "human-in-the-loop" methodologies.
nvidia houses the most forward-thinking minds in the world. are you a creative engineer ready to build the first truly self-verifying chip environment? come join our team and help us define the future of hardware powered by artificial intelligence.

we are now looking for a versatile, fast learner, and highly motivated fe integration and eda tools engineer! as a member of our switch organization, you will be part of frontend integration and eda flows for a highperformance, lowpower switch chip. our fei team drives methodologies, automation, and quality for our frontend implementation and cd/ci, working closely with architecture, design, verification, and backend teams. this position offers you the opportunity to have real impact in a dynamic, technologyfocused company influencing future switch product lines. 
what you'll be doing:
driving frontend integration of major blocks in a pioneering ethernet switch asic, from rtl handoff through synthesis and signoff checks.
building, maintaining, and improving eda flows and methodologies for the switch org (lint, cdc/rdc, formal, synthesis/uls, fedct/fefc and related frontend signoff flows).
working closely with logic design and microarchitecture teams to define integration constraints, clocks/resets, interfaces, and quality targets.
partnering with dv, be, and cad/flow teams to ensure robust, scalable, and efficient frontend implementation across the project.
developing automation and infrastructure (scripts, regression flows, dashboards) to improve productivity, and debuggability.
debugging complex tool, flow, and design issues; driving rootcause analysis and longterm methodology improvements.

we are looking for a formal Verification engineer for our nvidia networking team!
this is an exciting opportunity to join a hardworking pre-silicon design and verification team, working on groundbreaking switch and gpu technologies. we deploy state-of-the art formal verification tools and methodologies to prove design correctness. working in our formal verification team will expose you to a wide range of cutting edge design and technologies that are in the heart of th ai revolution. our team delivers world class chips solutions for hpc, ai infrastructures, data -center, network, and Storage markets. we micro-architect, verify, and deliver smart and high bandwidth multi port switches. nvidia has the most sophisticated formal tools and methodologies in the industry, which help us achieve a0 design tapeouts. as part of this team, you'll enjoy a versatile work environment, which is educational, dynamic and ambitious.
what you'll be doing:
in this position you will use formal verification algorithms to formally prove the correctness of complicated logic problems.
you will work on ambitious designs along with our pre-silicon team and take part in developing the next generation of nvidia's core technology.
you will take part in the ai revolution led by nvidia, working on cutting edge architecture.

our team in israel is looking for a dedicated chiplet sta owner to join us in defining the next era of ai's networking. this is an outstanding opportunity to work with innovative technology and collaborate with some of the most experienced minds in the industry. if you are ambitious, passionate about flawless design, and eager to make a lasting impact, this role is perfect for you!
what you'll be doing:
perform advanced static timing analysis (sta) at chiplet and fc level.
running prime time, review and debug timing paths, understand constraints, sdc generation, timing ecos generation.
identify convergence risks and work closely with physical design, rtl and dft teams, ensuring convergence throughout various project stages.
responsible for a full timing closer and quality approval from pre-layout sta model through signoff.

we are now looking for a senior chip design rtl design engineer for the switch silicon group.
as a chip design engineer at nvidia's networking business unit, you'll join a group of passionate engineers to design and implement the next generation state of the art switch silicon chips. in this position, you'll make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!
what you'll be doing:
work in a combined design and verification team which develops some of the switch silicon core units.
plan and design rtl units / blocks according to arch & micro arch specifications under challenging constraints with high orientation to power, area, and performance.
build reference models, verify and simulate chip blocks/entities according to specifications.
work closely with multiple teams within organizations such as architecture, micro- architecture, and fw.

we are looking for a power u-arch senior engineer. our company is known as a world leader in providing energy-efficient high-performance products and we continue to invest in the research and development of hyper-efficient SOC architectures. we are continually innovating in creative and unrivaled ways to improve our ability to deliver exceptional perf/watt solutions in a wide range of sectors and verticals. come join our applied power team to develop state of the art dpu products.
what you'll be doing:
lead a micro-architecture of power features such as: power management, logical power features, etc
work with dpu arch team on power features definition.
understand the workload characteristics for dpu workloads at system scale to drive new hw/sw features.