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we are looking for a ASIC Design Engineer.
Your Impact:
Write and review micro-architecture specifications
Implement RTL (Verilog/SystemVerilog) to meet timing, performance, and power requirements
Contribute to full chip integration, timing methodology, and analysis
Collaborate with verification engineers to resolve bugs and achieve coverage closure
Work with the physical design team to close timing and PnR issues
Support design methodology evolution and best practices
Perform debug, root-cause analysis, and post-silicon validation in the lab

Join the PHY system team, a pivotal part of silicon development. Our team focuses on the PHY and system aspects of our devices, including PHY firmware, calibrations, system definitions, operations, and post-silicon validation.
Key responsibilities include:
Working with the latest silicon technologies and processes to build large-scale, complex devices at the forefront of feasibility.
Contributing to the development of PHY firmware and system calibrations.
Participating in system definitions, operations, and post-silicon validation activities.

Join the PHY system team, a pivotal part of silicon development. Our team focuses on the PHY and system aspects of our devices, including PHY firmware, calibrations, system definitions, operations, and post-silicon validation.
Key responsibilities include:
Working with the latest silicon technologies and processes to build large-scale, complex devices at the forefront of feasibility.
Contributing to the development of PHY firmware and system calibrations.
Participating in system definitions, operations, and post-silicon validation activities.

we are looking for a Electrical Post Silicon Validation HW Engineer.
In this role, you will be part of the Switch ASIC Post-Silicon Electrical Validation (EPSV) team.
* Ensure the ASIC operates according to specifications and reliably over time by performing extensive, high-precision measurements using advanced test equipment and procedures.
* Conduct deep-dive investigations, integrating knowledge across hardware, software, and system domains to identify root causes of observed device behavior.
* Handle all chip validation aspects, including:
* Building validation plans.
* Performing EPSV using advanced test and measurement equipment.
* Writing tests in Python over device SDK.
* Executing tests and analyzing results.
You will gain in-depth knowledge of chip architecture, functionality, and operating modes, enabling you to debug and resolve electrical chip-related issues.

We are looking for an experienced STA Lead Engineer to join our growing BE team. We are working on the most challenging and interesting ASIC chips. Come join us and have a big impact on our groundbreaking and innovative designs.
Responsibilities
Take part in STA activities for blocks, Sub Systems and Full chip, from definitions to TO
Analyze timing results, verify correctness and provide timing budget for the different partitions.
Own the timing constraints both for STA and P&R flow.
Working closely with architecture, design, PD and DFT teams to make sure timing closure and ensures product success
Identify risks and bottlenecks, work closely with PD, RTL and DFT teams, ensuring convergence throughout various project stages.
Participating in design methodology, reviews and tool automation work and definition
As part of this rule you will gain very good understanding of our HPC and AI designs and sub system as well as product targets.

We are looking for a talented and experienced engineer to participate in the physical design of the companys product for leading one of Nextsilison BE projects. This position involves working with external back-end developers as well as carrying out critical tasks in-house, and leading aggressive back-end initiatives to meet challenging targets in terms of area, timing, and layout.
In this role, you will be at the center of the companys design efforts and will have a significant influence on product architecture.
Responsibilities
Generate and analyze critical block- and chip-level static timing constraints
Spec and define full chip floor plan, including pin placement, partitions, and power grid
Develop and validate high-performance, low-power clock network guidelines
Perform critical block-level place and route and create designs that meet timing, area, and power constraints
Review the vendors physical design verification flow at chip and block level and guide other designers on how to fix LVS and DRC violations
Work with vendors on defining physical design methodologies and assist in flow development for chip integration.

We are looking for a talented and experienced engineer to participate in designing the next era of computer architecture. In this position you will take part in designing the critical parts of our future chips. You will transform architectural requirements to micro-architectural specs, implement key blocks in RTL, and participate in post-silicon activities.
Everything we do is guided by three core values:
Professionalism: We strive for exceptional results through professionalism and unwavering dedication to quality and performance.
Unity: Collaboration is key to success. That's why we foster a work environment where every employee can feel valued and heard.
Impact: We're passionate about developing technologies that make a meaningful impact on industries, communities, and individuals worldwide.
Responsibilities
Define and drive the design of advanced blocks from micro-architecture phase to netlist
Support timing and constraints definitions work closely with the BE team on timing and physical implementation efforts
Leading processes relating to power optimization
Technology expert, building a knowledge base for the group
Work with various teams to drive execution (SW, Architecture, verification, BE, etc)
Devise execution indicators and monitor and report execution progress to enable prioritization and clear decision making.

We are looking for a talented and experienced engineer to take part in the Emulation and Prototyping efforts for the companys core product.
This position involves building a complex emulation environment from scratch, and collaborating with software, design, and verification teams. In this role, you will be leading emulation from A to Z and will have a critical impact on the company.
Responsibilities
Develop and build complex emulation models for coming generations of our accelerators, including transactors like PCIe, SPI, and embedded CPUs
Work with the software, design, development, and verification teams to understand the functional and performance goals of the products design
Optimize the model for speed and capacity and develop debug abilities to support software and firmware teams
Work with software design and development teams to define and develop BFM, test bench, and checker tools
Review specifications and develop attributes, tests, and coverage plans for the emulation system.

We are seeking an exceptional architect to join our architecture team and shape the future of quantum control. We have a unique opportunity to set the architecture of the next-generation quantum computers towards utility scale quantum computing.
In this role, you will lead the architecture definition of the next generation quantum control system, from units/building blocks roles and responsibilities, core components such as DACs/ADCs, FPGAs, communication interfaces and power and cooling solutions .Designing a scalable architecture of quantum control requires deep understanding of quantum computing, system tradeoffs and product requirements. In this role, youll work closely with Product to define the hardware requirements and an architecture to address them. Youll identify system level tradeoffs, identify solutions alternatives and define POCs to evaluate them. In your role youll be working closely with all R&D teams, in particular the system, hardware and logic teams and with partners in the industry.
Responsibilities:
Architecture for the next generation quantum control system and hardware
Define system-level architecture and features, providing detailed specifications to the various R&D teams.
Collaborate with the product and research to transform high level requirements into architecture and spec definitions and presenting tradeoffs
Collaborate with the architecture team members to consolidate requirements and implications for the software and logic architecture
Work with partners and vendors on requirements and joint development to optimize the product capabilities
Define requirements for research activities and for proof-of-concepts for new architecture and technical capabilities.

we are a global leader in control systems for quantum computing, a field on the verge of exponential growth.
Our innovative hardware and software mark a groundbreaking approach in quantum computer control, scaling from individual qubits to expansive arrays of thousands.
At the core of our company lies a passionate and ambitious team committed to reshaping the construction and operation of quantum computers.
Our work is fueled by a deep understanding of customer needs, driving us to deliver unparalleled solutions in this revolutionary field.
Join our cutting-edge hardware development team as Micro-Architect and play a key role in defining and implementing the micro-architecture of advanced digital logic components.
What You'll Do:
Define and develop micro-architecture for complex logic blocks - from concept through high-quality RTL implementation
Collaborate closely with architecture, verification, design and software design teams
Write clear and detailed design specifications and drive architectural trade-off analysis
Optimize for performance and area
Contribute to innovation, methodology improvements, and technical leadership within the team.

We are driving innovation in automotive technology, developing solutions that power the next generation of vehicles. We are looking for a Junior Engineer who is eager to learn, grow, and make an impact in a dynamic and innovative environment. This is a unique opportunity to work alongside experienced professionals, gain hands-on experience, and contribute to projects at the forefront of automotive electronics. If you are passionate about technology, curious to explore new challenges, and excited to make a real difference, we are the place to develop your skills, innovate, and grow your career.
Why join us?
* Work on cutting-edge automotive projects.
* Learn from a talented and supportive team.
* Gain exposure to real-world automotive challenges.
* Grow your career in a collaborative and inspiring environment.
If youre ready to take the next step in your career and be part of something meaningful, wed love to meet you!
About The Position:
As a Junior ASIC Design Engineer, you will take part in the full lifecycle of advanced chips that power the next generation of vehicles. This is a hands-on, growth-oriented role where youll work closely with experienced ASIC engineers, gain exposure to real silicon, and build a strong foundation in chip design and verification. In this role, you will:
* Be part of a professional ASIC team working on cutting-edge automotive solutions.
* Support and learn from real emulation platforms used in production-grade designs.
* Contribute to RTL implementation and gain practical experience in design flows.
* Assist with verification and backend (BE) activities, learning industry best practices.
* Participate in silicon bring-up, seeing your work come to life on real hardware This position is ideal for curious engineers who want to learn fast, take ownership, and grow into a key contributor in the world of automotive semiconductor design.

Power the Future with us! At SolarEdge (NASDAQ: SEDG), we're a global leader in smart energy technology, with over 3,000 employees, offices in 34 countries, and millions of installations worldwide. Our innovative solutions include solar inverters, battery storage, backup systems, EV charging, and AI-based energy management. We're committed to making clean, green energy the primary power source for homes, businesses, and beyond. With the growing demand for electricity, the need for smart, clean energy sources is constantly rising. SolarEdge offers amazing opportunities to develop your skills in a multidisciplinary environment, covering everything from research and development to production and customer supply. Work with talented colleagues, tackle exciting challenges, and help create a sustainable future in an industry that's always evolving and innovating. Join us and be part of a company that values creativity, agility, and impactful work. We are looking for a Senior ASIC Verification engineer with good grasp of the entire verification process – plan, execution and sign-off, excellent analytical skills, technical skills and high motivation to join our team and take part of the success. What you will be doing:
* Create a thorough verification plan out of IP specification and implement it to completeness.
* Build UVM-compliant IP verification environment from scratch.
* Debug to find root cause of issues.
* Full-chip verification from planning stage to tape-out, including gate-level testing.
* Testing using both System Verilog and C.
* Work in a diverse environment, collaborating with power engineers, communication experts and SW developers

Country:
Israel

City:
Herzliya

Power the Future with us! At SolarEdge (NASDAQ: SEDG), we're a global leader in smart energy technology, with over 3,000 employees, offices in 34 countries, and millions of installations worldwide. Our innovative solutions include solar inverters, battery storage, backup systems, EV charging, and AI-based energy management. We're committed to making clean, green energy the primary power source for homes, businesses, and beyond. With the growing demand for electricity, the need for smart, clean energy sources is constantly rising. SolarEdge offers amazing opportunities to develop your skills in a multidisciplinary environment, covering everything from research and development to production and customer supply. Work with talented colleagues, tackle exciting challenges, and help create a sustainable future in an industry that's always evolving and innovating. Join us and be part of a company that values creativity, agility, and impactful work. We are looking for a Senior ASIC Verification engineer with good grasp of the entire verification process – plan, execution and sign-off, excellent analytical skills, technical skills and high motivation to join our team and take part of the success. What you will be doing:
* Create a thorough verification plan out of IP specification and implement it to completeness.
* Build UVM-compliant IP verification environment from scratch.
* Debug to find root cause of issues.
* Full-chip verification from planning stage to tape-out, including gate-level testing.
* Testing using both System Verilog and C.
* Work in a diverse environment, collaborating with power engineers, communication experts and SW developers.

Country:
Israel

City:
Herzliya

We are looking for a Senior Algorithm engineer to join a high-velocity R&D team developing advanced Real-Time algorithms for mission-critical defense systems. The role focuses on designing, implementing, and evolving estimation, inference, and decision algorithms that operate under real-world constraints such as uncertainty, latency, partial observability, and adversarial conditions. You will take ownership of core algorithmic components from theoretical formulation through deployment in operational systems.
Responsibilities:
Design, implement, and maintain Real-Time estimation and inference algorithms operating on heterogeneous sensor inputs. Develop and tune probabilistic state-estimation models, including non-linear filters, adaptive models, and prediction mechanisms. Implement uncertainty management, gating, clustering, hypothesis handling, and state lifecycle logic. Integrate AI/ML components where they provide measurable value (classification, anomaly detection, decision support). Own algorithm performance across stability, convergence, latency, and numerical robustness metrics. Translate operational and system -level needs into mathematical formulations and deployable algorithms. Collaborate closely with system engineers and software teams to integrate algorithms into Real-Time command-and-control environments. Analyze operational data, simulations, and edge cases; iteratively refine models based on empirical performance. Participate in algorithm design reviews, trade-off analyses, and performance assessments.