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Our Systems Group is looking for a Systems Engineer to join the Integrated Metrology team, a multidisciplinary group of physicists and engineers working together to implement cutting-edge metrology technologies in the semiconductor industry from a unique and innovative perspective.
Responsibilities
What you will be doing:
Perform theoretical and experimental systems engineering to support state-of-the-art new and existing multidisciplinary optical measurement products
Drive the full lifecycle from customer needs through feasibility and concept evaluation, leading to cross-disciplinary system requirements, while defining and managing system KPIs
Conduct laboratory and on-site system diagnostics, troubleshooting, and problem-solving, including root-cause analysis, mitigation plans, implementation of robust system calibration methods, and product transfer to manufacturing
Work closely with multiple disciplines, including physics, optics, algorithms, mechanics, electronics, and software
Translate customers high-level requirements into detailed technical specifications
Travel to customer sites worldwide (2-3 times per year).

The Production team is looking for a Production Integration Engineer to join the integrated metrology line and work on state of the art tools in the semiconductor industry.
Your role will be to manufacture the company products while maintaining highest quality and on-time delivery.
As part of your job you will interact and work with the Engineering, R&D and QA departments to solve complicated on tool problems and test new tools and features as part of the transfer to production process.
Responsibilities
What will you be doing:
Lead tool manufacturing process from start to end (1-2 weeks project).
Integration of multidisciplinary systems (optical, electronic, pneumatic, computing, and mechanical) according to predefined procedures.
Ability to solve complex system challenges, constantly learning and striving to independence.
Working with engineering and R&D to address systems/production process challenges.
Addressing quality issues and repair recommendations for suppliers by nonconformance report.
Working in an organized way using digital procedures and flow management system.
Always striving to reduce cycle time and improve working process.
Helping and consulting team members to overcome challenges on their tools.

We are seeking a Motion Control Engineer to develop complex metrology systems for ultra-high-precision measurements of semiconductor manufacturing processes.
These systems incorporate high-end performance motion devices whose development requires proficiency in motion control systems.
In this role, you will join our Motion Control group. You will be designing, developing, and implementing advanced motion systems for the next-generation Optical Critical Dimension metrology tools, as part of a world-class R&D division.
Responsibilities
What will you be doing:
Develop and implement unique solutions that integrate advanced motion control technologies, delivering innovative and out-of-the-box approaches using cutting-edge, high-end technology.
Leverage strong engineering expertise to develop and optimize servo control systems, including algorithm design and custom solution implementation.
Analyze and optimize motion control system performance to ensure compliance with specifications and stability requirements.
Take ownership of suppliers and manufacturers, define equipment specifications, and stay up to date with the latest technological developments.
Present and explain product specification definitions and design reviews from a motion and electronics engineering perspective.
Conduct testing, inspection, and troubleshooting of motion control and electronics modules and subsystems.
Collaborate closely with R&D teams on motion control and servo solutions, supporting lab setups, prototypes, and jigs.

As a Wireless Design Verification Engineer, you will be part of a team that is responsible for pre-silicon RTL verification of communication subsystems, SoC sub-systems and chip-level functionality. The activity may focus on block level, sub-system level or chip level, including end-to-end simulations of the entire data/control path. You will interact with DV methodologists, designers and communication systems engineers to develop reusable testbench and verification environment deploying the latest methodology with metric driven verification.
Description
- Own critical block and sub-system verification of wireless SoC projects
- Architect and develop testbenches and environments, by using state-of-the-art verification methodologies
- Define verification plan, create, simulate and debug test scenarios
- Drive regression and coverage analysis to ensure high quality DV
- Collaborate with design and systems engineering teams to review requirements, specifications and architecture, extract features and define DV attribute

We are seeking an experienced System Engineer with a strong background in electro-optics to join our innovative and multidisciplinary team. This role involves leading system-level design and integration of advanced electro-optical systems that combine optics, mechanics, electronics, and algorithms.
Responsibilities
Contribute to the design and architecture of advanced electro-optical systems.
Collaborate closely with a multidisciplinary team, including software, firmware, hardware, mechanical, and algorithm engineers, as well as product managers.
Conduct hands-on evaluation and testing of optical components and prototypes using optical and software tools.
Lead system integration activities and troubleshooting throughout development and production stages.
Oversee deployment of complex, multi-disciplinary systems into mass production.
Prepare and maintain system-level documentation, including architecture definitions, specifications, test plans, and performance reports.

Required Radar Systems Engineer.

The Junior / Trainee Instrumentation and Electrical Technician supports the installation, calibration, maintenance, and troubleshooting of instrumentation, control and electrical systems used in oil and gas operations. This role is designed for entry-level candidates and focuses on developing technical skills while working under close supervision of senior technicians, ensuring safe and reliable plant operations.

Ashdod, Southern District

Demonstrates ability to monitor and operate plant equipment and conduct routine duties and non-routine Operations activities.

Maintain a clean and organized work environment to identify hazards.

Toolbox talk and last-minute risk assessment using COW processes for a specific activity.

Demonstrates basic technical competencies and capabilities in upstream/ midstream/ downstream and manufacturing plant operations, including pipeline and hydrocarbon behavior

Demonstrates ability to troubleshoot and solve basic operational problems by teaming and collaborating with cross-functional teams

Supports and properly responds to unplanned events and their impact on equipment and operations.

Comply with the Companys safety standards, policies, and regulatory requirements

Identify and describe basic step-by-step maintenance requirements in Gas and chemical streams

Report and identify the source of surface staining on tanks and equipment.

Maintain, record, and inventory production supplies

It has basic ability to read/interpret/field as-built P&IDs, SAFE Charts, Cause & Effects.

Basic abilities to analyze trends of efficiency degradation on production equipment

Performs basic analysis of Process Safety Management (PSM)

Utilization of computerized systems, including SAP, D2 (document control), Enablon (E-PTW), and Bluebeam Revu.

Execute and understand MOC and RIK processes

Execute level 1 and level 2 Hazard analysis in general work, breaking containment, isolation of hazardous energy, bypass critical protection, and stop work authority to ensure safe operation.

This position is responsible for interpreting Control Philosophies, Cause & Effects, P&IDs and developing, testing, documenting, and maintaining Rockwell ControlLogix PLC & FactoryTalk HMI based systems and Archestra System Platform object-based programs, templates, processes, and tools to manage and sustain programming code for offshore and high-pressure gas production facilities. Supports project activities including facility design, construction, commissioning, troubleshooting, managing, and maintaining SCADA, DCS, SIS, HMIs, PLCs, PCN Servers & Applications and Communication systems reliability and availability. Maintains SCADA data reporting systems, support Operations production reliability and optimization efforts and support PCN Information Risk Management (IRM) compliance. Train and mentor Operations and Maintenance personnel.

As a Design Verification Manager for the IP Group, you will lead a focused team responsible for the quality and reliability of our critical IP blocks. You will steer the IP verification roadmap, oversee the development of complex testbenches, and ensure our next-generation AI silicon meets the highest standards. Leading a team of talented engineers, you will tackle challenges at the unit and sub-system levels, playing a pivotal role in delivering high-performance hardware for the worlds largest AI clusters.

Key Responsibilities



Lead and mentor a team of design verification engineers, defining the technical roadmap and methodology for ASIC verification across unit and IP/sub-system levels
Drive the creation and execution of comprehensive design verification plans, ensuring all functional requirements are met on schedule for complex digital IPs
Oversee the architecture and maintenance of block-level verification strategies, heavily utilizing SV-UVM, alongside Formal Verification where applicable
Define functional coverage goals and quality metrics, driving the IP team toward 100% verification closure and sign-off
Partner closely with IP Design and Architecture teams to align on specifications, root-cause complex bugs, and optimize the IP development cycle

As an Expert EMIR & Power Integrity Lead, you will be a core technical contributor ensuring the power robustness and long-term reliability of our high-performance connectivity silicon. You will own from block level to full-chip the Electro-Migration and IR Drop (EMIR) methodology, analysis, and sign-off, working at the intersection of Physical Design, Analog/Mixed-Signal design, and Package Engineering.

You will be responsible for defining power grid architectures and validating that products meet aggressive voltage drop and reliability targets in advanced FinFET process nodes. Your work will directly impact the performance and yield of chips operating in the worlds most demanding AI and cloud environments.

Key Responsibilities

Lead static and dynamic IR drop analysis, signal/power electromigration (EM) verification, and self-heat analysis from block level to full-chip sign-off
Define and implement robust EMIR flows and methodologies using industry-standard tools (Ansys RedHawk-SC, Cadence Voltus, or equivalent)
Collaborate with Physical Design teams to define optimal power grid structures, via pillars, and strap distributions to minimize voltage drop while maximizing routing resources
Work closely with Analog/SerDes designers to analyze current profiles and ensure robust power delivery to sensitive high-speed IP blocks
Partner with Package Design engineers to perform Chip-Package-System (CPS) co-analysis, optimizing bump patterns and package routing for superior Power Integrity
Drive root-cause analysis for voltage drop violations and EM risks; propose and implement layout fixes alongside the PD team
Verify current density rules for ESD protection networks and ensure compliance with foundry reliability constraints
Support silicon bring-up by correlating simulation results with actual silicon measurements and yield data

we're seeking a visionary Expert IC Package Design Lead to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, leading the physical implementation strategy for chips that power the world's largest AI clusters.

As an Expert IC Package Design Lead, you will be a core technical contributor in the development of advanced IC packaging solutions for high-performance connectivity silicon.
You will own package flow, architecture, design, and qualification from concept through production, working closely with silicon, signal integrity, power integrity, mechanical, manufacturing, and external OSAT partners.You will be responsible for defining package technologies that meet aggressive electrical, thermal, mechanical, and cost targets, enabling products to operate reliably in the worlds most demanding AI and cloud environments.

Key Responsibilities

Own end-to-end IC package design, from early architecture and feasibility through detailed design, qualification, and high-volume manufacturing
Define package architecture and technology selection (organic substrates, advanced laminate, interposers, multi-die/chiplet packaging, CoWoS - 2.5D/3D integration)
Lead signal integrity (SI), power integrity (PI), and thermal considerations at the package level for high-speed, high-power devices
Drive package layout, substrate routing, bump/ball maps, stack-ups, materials selection, and mechanical constraints
Collaborate closely with silicon design, SerDes, system, SI/PI, and reliability teams to optimize overall product performance
Interface with OSATs, substrate vendors, and manufacturing partners to ensure design-for-manufacturability (DFM), yield, and cost targets
Lead package-related risk assessment, failure analysis, and corrective actions during bring-up and production ramp
Support NPI, qualification, and product sustainment activities, including vendor audits and technical reviews

As the Physical Design Chip Top Expert you will be a Key member of our PD Team in Israel R&D center. You will run PD execution of SoC Top level for chips that drive the worlds largest AI clusters. As PD Top Level Lead, you will own all PD disciplines of the Chip and own the T.O GDS that meet the chip signoff Criteria (Timing, LVS, EMIR, DRC, PV etc. ) ensuring our silicon meets the extreme performance, power, and area (PPA) targets required for AI scale.

Key Responsibilities

SoC Top level Ownership and oversee the Chip convergence.
Take full ownership of Top Level physical implementation, including floor planning, P&R, CTS, Power/Clock distribution, Power integrity and Timing/Physical signoff
Work closely with the Architecture, Design, DFT, and Product teams to achieve optimal Power Performance Area (PPA). This involves conducting feasibility studies for new architectures and optimizing runs to ensure the best Quality of Results (QoR)
Address complex signal integrity, thermal, and power challenges inherent in high-speed connectivity silicon
Work Closely with Package team on Bump map to Ballout taking into consideration all Signal integrity aspects