לוח משרות דרושים הייטק

we are looking for a Senior Data & Business Analyst to lead analytics and business health indicators across our operational and company-wide domains. This is a senior individual contributor role combining strategic thinking, deep hands-on analytical execution, and strong cross-functional business partnership. Youre welcome to work in our office in Tel Aviv.
The role requires the ability to operate at two levels simultaneously: understanding the full business picture while diving deep into complex datasets and technical execution. You will work closely with Operations, Finance, and other cross-functional teams to improve efficiency, transparency, and decision-making across the organization.
Your responsibilities will include:
Own end-to-end analytics for core operational processes.
Define, build, and maintain company-level operational and business health KPIs.
Translate ambiguous, cross-functional business questions into structured analytical frameworks.
Write advanced, high-performance SQL to extract, model, and analyze complex datasets.
Lead deep-dive analyses to uncover operational inefficiencies, financial impact, and process gaps.
Connect data across systems and explain upstream and downstream business impact.
Independently identify high-impact problems worth solving, not only respond to requests.
Drive cross-functional analytical initiatives at a company-wide level.
Present insights, trade-offs, and recommendations to senior leadership.
Synthesize complex findings into concise executive-level narratives.
Influence decisions and drive measurable impact based on data.
Act as a central analytical partner across multiple business domains.
Lead initiatives and move stakeholders forward without direct authority.

we are leading the global shift to additive manufacturing with innovative 3D printing solutions for industries such as aerospace, automotive, consumer products and healthcare. Through smart and connected 3D printers, polymer materials, a software ecosystem, and parts on demand, our company solutions deliver competitive advantages at every stage in the product value chain. The worlds leading organizations turn to our company to transform product design, bring agility to manufacturing and supply chains, and improve patient care.
The Senior Campaign Manager, Digital Paid Media & Demand Generation is a pivotal role that requires an equal balance of strategic ownership (50%) and deep, hands-on campaign execution (50%). This role demands a seasoned B2B marketer who not only defines sophisticated, data-driven strategies but also thrives on being the primary daily user and optimizer within the paid media platforms and Account-Based Marketing (ABM) execution channels to drive measurable pipeline and revenue impact.
This position requires moving seamlessly between designing the quarterly campaign roadmap and managing granular bidding strategies, audience segments, and personalized ABM plays on a daily basis.
Essential Duties & Responsibilities
The responsibilities are split into an equal 50% Strategic Leadership & Analysis and 50% Direct, Hands-on Execution & Optimization.
Strategic Leadership & Analysis (50%)
Paid Media Strategy Development: Design and own the integrated, full-funnel paid media strategy (awareness / consideration / conversion) that directly supports global B2B demand generation and ABM objectives.
ABM Strategy & Framework: Lead the strategic development of Account-Based Marketing (ABM) demand generation, including defining target account lists, personalized campaign frameworks, and measurement approaches that drive engagement within key accounts.
Budget & Channel Prioritization: Guide prioritization of channels, budgets, and audience segmentation based on performance data, market insights, and strategic business goals.
Performance Measurement & Insights: Proactively analyze performance trends and develop comprehensive testing roadmaps (A/B testing, audience variations, bid strategies) to maximize ROI across both broad campaigns and targeted ABM initiatives.
Cross-Functional Alignment: Collaborate with stakeholders across Product Marketing, Content, Creative, and Sales to ensure campaign messaging, assets, and goals are fully aligned and optimized.
Direct, Hands-on Execution & Optimization (50%)
Direct Paid Media Platform Management (MANDATORY): Serve as the primary, hands-on owner for building, launching, monitoring, and optimizing all digital paid media campaigns.
Core Platforms: Google Ads (Search, Display, YouTube), LinkedIn Ads, Meta Ads (Facebook/Instagram), and potentially others.
Hands-on ABM Execution (MANDATORY): Own day-to-day execution of ABM programs, including launching, monitoring, and optimizing personalized ad campaigns, content syndication to target lists, and account-specific digital plays using native ad tools and other channel capabilities.
Full Campaign Ownership: Responsible for end-to-end execution, including:
Audience Creation: Developing and implementing granular audience segmentation (lookalikes, custom audiences, retargeting lists) and uploading/managing precise Target Account Lists for ABM campaigns.

We are looking for a highly skilled SW developer Expert with substantial Object-Oriented experience in a multi-disciplinary environment to join our R&D group in Israel (Rehovot).
You will be a part of a talented software team that is currently developing the next generation of 3D printers, using cutting-edge technology and constantly looking for new ideas and improvements.
What you will be doing:
Lead development tasks through all stages - gathering requirements, designing, implementing (mostly using C++ and C#) and following integration on the 3D printers themselves.
Work closely with System and HW engineers, SW developers, QA and many more.
Perform design and code reviews
Constant collaboration and knowledge sharing with the SW team.

We are seeking an experienced Cybersecurity Manager to oversee a global cybersecurity team. This role is responsible for protecting enterprise systems, networks, and data, driving security initiatives, ensuring regulatory compliance, and managing cyber risk across the organization.
Key Responsibilities:
Lead daily operations of the cybersecurity team, ensuring high levels of performance and service.
Execute, implement, and enforce cybersecurity strategies, standards, and policies.
Manage security incident response, threat detection, vulnerability management, and risk mitigation.
Collaborate closely with IT, Compliance, Legal, and Executive teams to align security initiatives with business needs.
Drive adoption and optimization of Microsoft 365 security tools and services.
Ensure secure configuration and management of Active Directory, Azure AD, Windows Server, DNS, DHCP, and related systems.
Support cybersecurity audits, compliance programs, and regulatory reporting efforts.
Mentor and develop cybersecurity staff, promoting continuous improvement and skill advancement.
Stay informed on emerging threats, technologies, and regulatory changes.

we are looking for a strategic and analytical Senior Compensation & Benefits Partner to lead Total Rewards across EMEA & APAC.
In this role, you will design, implement, and manage competitive and compliant compensation and benefits programs, while partnering closely with regional leaders and the global Total Rewards team. Youll balance global consistency with local market expertise and play a key role in shaping our employee value proposition across diverse markets.
What Youll Do
Compensation Leadership
Lead regional merit, bonus, equity, and promotion cycles
Provide guidance on hiring, mobility, promotions, and retention
Conduct market pricing and compensation modeling
Partner on job architecture and leveling frameworks
Ensure compliance with pay transparency and labor regulations
Benefits Strategy & Management
Oversee health, retirement, wellness, and insurance programs across EMEA & APAC
Lead renewals and vendor partnerships
Support global harmonization while respecting local requirements
Governance & Compliance
Ensure compliance with local labor and tax regulations
Maintain documentation, controls, and audit readiness
Monitor regulatory changes and assess program impact
Business Partnership
Serve as the primary Total Rewards partner for HR and business leaders in the region
Translate complex compensation topics into clear guidance
Support manager enablement and employee education
M&A & Integration
Support compensation and benefits due diligence for mergers and acquisitions
Lead Total Rewards integration planning and post-merger harmonization (PMI).

As a Design Verification Manager for the IP Group, you will lead a focused team responsible for the quality and reliability of our critical IP blocks. You will steer the IP verification roadmap, oversee the development of complex testbenches, and ensure our next-generation AI silicon meets the highest standards. Leading a team of talented engineers, you will tackle challenges at the unit and sub-system levels, playing a pivotal role in delivering high-performance hardware for the worlds largest AI clusters.

Key Responsibilities



Lead and mentor a team of design verification engineers, defining the technical roadmap and methodology for ASIC verification across unit and IP/sub-system levels
Drive the creation and execution of comprehensive design verification plans, ensuring all functional requirements are met on schedule for complex digital IPs
Oversee the architecture and maintenance of block-level verification strategies, heavily utilizing SV-UVM, alongside Formal Verification where applicable
Define functional coverage goals and quality metrics, driving the IP team toward 100% verification closure and sign-off
Partner closely with IP Design and Architecture teams to align on specifications, root-cause complex bugs, and optimize the IP development cycle

As an Expert EMIR & Power Integrity Lead, you will be a core technical contributor ensuring the power robustness and long-term reliability of our high-performance connectivity silicon. You will own from block level to full-chip the Electro-Migration and IR Drop (EMIR) methodology, analysis, and sign-off, working at the intersection of Physical Design, Analog/Mixed-Signal design, and Package Engineering.

You will be responsible for defining power grid architectures and validating that products meet aggressive voltage drop and reliability targets in advanced FinFET process nodes. Your work will directly impact the performance and yield of chips operating in the worlds most demanding AI and cloud environments.

Key Responsibilities

Lead static and dynamic IR drop analysis, signal/power electromigration (EM) verification, and self-heat analysis from block level to full-chip sign-off
Define and implement robust EMIR flows and methodologies using industry-standard tools (Ansys RedHawk-SC, Cadence Voltus, or equivalent)
Collaborate with Physical Design teams to define optimal power grid structures, via pillars, and strap distributions to minimize voltage drop while maximizing routing resources
Work closely with Analog/SerDes designers to analyze current profiles and ensure robust power delivery to sensitive high-speed IP blocks
Partner with Package Design engineers to perform Chip-Package-System (CPS) co-analysis, optimizing bump patterns and package routing for superior Power Integrity
Drive root-cause analysis for voltage drop violations and EM risks; propose and implement layout fixes alongside the PD team
Verify current density rules for ESD protection networks and ensure compliance with foundry reliability constraints
Support silicon bring-up by correlating simulation results with actual silicon measurements and yield data

As the Physical Design Chip Top Expert you will be a Key member of our PD Team in Israel R&D center. You will run PD execution of SoC Top level for chips that drive the worlds largest AI clusters. As PD Top Level Lead, you will own all PD disciplines of the Chip and own the T.O GDS that meet the chip signoff Criteria (Timing, LVS, EMIR, DRC, PV etc. ) ensuring our silicon meets the extreme performance, power, and area (PPA) targets required for AI scale.

Key Responsibilities

SoC Top level Ownership and oversee the Chip convergence.
Take full ownership of Top Level physical implementation, including floor planning, P&R, CTS, Power/Clock distribution, Power integrity and Timing/Physical signoff
Work closely with the Architecture, Design, DFT, and Product teams to achieve optimal Power Performance Area (PPA). This involves conducting feasibility studies for new architectures and optimizing runs to ensure the best Quality of Results (QoR)
Address complex signal integrity, thermal, and power challenges inherent in high-speed connectivity silicon
Work Closely with Package team on Bump map to Ballout taking into consideration all Signal integrity aspects

As a Physical Design CAD Lead, you will be responsible for the physical implementation environment. Your primary mission is to build, optimize, and support the automated flows from RTL to manufacturable GDSII tape-out. You will own the flows, Database and will support the whole PD team to optimize their blocks for Power, Performance, Timing while keep the team aligned on Methodical, Efficient and balanced work Environment.


Key Responsibilities

Design and maintain automated flows for Synthesis, Place & Route, and Floor-planning
Develop robust environments for Static Timing Analysis, Power Analysis, and Physical Verification (DRC/LVS/ERC)
Write custom plug-ins and scripts to extend the capabilities of vendor tools, tailoring them to our specific process node constraints and flows
Create automated "dashboards" and feedback loops to help design teams track and improve Power, Performance, and Area metrics across iterations
Collaborate with EDA vendors (Synopsys, Cadence, Siemens/Mentor) as consulters for our developed flows and results analysis     

we're seeking a visionary Physical Design Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the backend execution and methodologies for chips that power the world's largest AI clusters.

As a Physical Design Engineer, you will be a key architect of our silicon's physical reality. You won't just execute a flow-you will help establish our local execution culture and technical standards, owning the transformation of complex logic into high-performance silicon. You will drive the physical implementation journey from synthesis through signoff, ensuring our connectivity solutions meet the extreme performance, power, and area targets required for next-generation AI infrastructure. If you thrive on solving complex challenges in deep-submicron processes and want to shape the backend methodology for AI infrastructure connectivity, this is your opportunity.

Key Responsibilities

Physical Implementation & Execution

Be part of the founding Backend team in Israel, playing a critical role in establishing local execution culture and technical standards
Take full responsibility for physical implementation journey including Synthesis, Floorplanning, Place & Route, and Clock-Tree Synthesis (CTS)
Own macro-level implementation with deep hands-on experience in floorplanning and complex routing
Signoff & Design Integrity

Drive final stages of design integrity, owning Timing signoff (STA), Physical Verification (DRC/LVS), and Reliability analysis (EMIR)
Ensure first-pass silicon success through rigorous signoff flows and analysis
Apply Logic Equivalence Checking (LEC) and other verification techniques to guarantee design correctness
Methodology Development & Cross-Functional Collaboration

Participate in defining and refining Backend methodologies with autonomy to improve workflows and tool automation
Work closely with Architecture, Design, and DFT teams to navigate challenges of advanced process nodes and high-speed connectivity
Leverage scripting and automation to make engineering environment faster and more robust

we're seeking a visionary Physical Design Subsystem (Multiple IPs/Partitions) Lead to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the backend execution and methodologies for chips that power the world's largest AI clusters.

If you thrive on solving complex, unnamed challenges in deep-submicron processes, your place is with us.

As the Physical Design Subsystem (Multiple IPs/Partitions) Lead you will be a Key member of our PD Team in Israel R&D center. You will run PD execution of SubSystem with your team for chips that drive the worlds largest AI clusters. You will lead the team and the transition from RTL to GDS, ensuring our silicon meets the extreme performance, power, and area (PPA) targets required for AI scale.

Key Responsibilities

Build and mentor a high-performing Partitions team , owning the end-to-end execution from Synthesis to Signoff
Take full ownership of Subsystem physical implementation, including floorplanning, P&R, CTS, Power/Clock distribution, Power integrity and Timing/Physical signoff
Work closely with the Architecture, Design, DFT, and Product teams to achieve optimal Power Performance Area (PPA). This involves conducting feasibility studies for new architectures and optimizing runs to ensure the best Quality of Results (QoR)
Lead and guide external contractors and global partners to ensure seamless execution and delivery
Address complex signal integrity, thermal, and power challenges inherent in high-speed connectivity silicon

As a Principal/ Senior Principal ASIC Architect, you will be the blueprint creator for the future of AI infrastructure. You won't just follow specifications-you will lead the definition and execution of next-generation ASIC solutions targeting hyperscale data centers. From analyzing market requirements to guiding products through their entire lifecycle, your influence will be etched into the silicon that enables the next era of scale-up and scale-out connectivity. If you thrive on solving complex, unnamed challenges and want to shape the architectural foundation of AI infrastructure connectivity, this is your opportunity.

Key Responsibilities

Architectural Definition & Strategy

Lead the architectural definition of next-generation ASICs, translating complex market requirements into elegant, high-performance hardware specifications
Drive technical decision-making that balances power, performance, area, and cost (PPAC) to maintain competitive edge in the hyperscale ecosystem
Leverage deep domain expertise to integrate industry standards (Ethernet, UALink, PCIe) into cohesive systems solving demanding AI infrastructure challenges
Product Lifecycle Ownership

Own the architectural journey from initial concept through design, implementation, tapeout, and mass production
Ensure final products deliver on performance promises and meet hyperscaler requirements
Drive architectural exploration and performance modeling to validate design decisions
Technical Leadership & Cross-Functional Collaboration

Act as the technical North Star for the engineering organization in Israel
Collaborate across Architecture, Design, Verification, DFT, and Backend teams to ensure seamless execution
Influence and align cross-functional teams around unified technical vision through strong communication and leadership

As a Senior ASIC Design Engineer, you won't just build chips-you will be part of a team defining the next generation of AI infrastructure main components. The complex digital blocks under your micro-architecture and implementation responsibilities will power the world's largest AI clusters. You will own the journey from high-level definition through RTL implementation and backend support, transforming complex logic challenges into elegant, high-performance hardware. If you thrive on solving challenging problems in deep-submicron processes and want to contribute to the digital design foundation for AI infrastructure connectivity, this is your opportunity.

Key Responsibilities

Design Ownership & Implementation

Own the journey from high-level definition through micro-architecture, coding, and debug to backend implementation support
Tackle complex logic challenges and transform them into elegant, high-performance hardware solutions
Serve as the point of contact for your logic blocks, interacting with Architecture, Verification, and Backend teams
Quality Assurance & Design Optimization

Utilize industry-leading EDA tools (Lint, CDC, Synthesis, Timing, Power) and in-house quality assurance tools to ensure designs are robust, scalable, and power-efficient
Apply design techniques to meet PPA (Power, Performance, Area) targets
Contribute to design quality through verification and validation activities
Methodology Innovation & Collaboration

Participate in design methodology improvements and tool automation initiatives
Leverage AI assistance tools and contribute to in-house automation development to make engineering workflows faster and smarter
Collaborate effectively across teams to ensure seamless integration

As an Senior Emulation Engineer, you will be a core technical driver of our Israel R&D center, working at the intersection of hardware and software to ensure our silicon meets extreme quality and performance targets. You will execute end-to-end emulation flows, bridge the gap between RTL and functional validation, and partner with cross-functional teams to enable seamless hardware-software integration. If you thrive on solving complex technical challenges and want to play a key role in validating cutting-edge AI infrastructure connectivity solutions, this is your opportunity.

Key Responsibilities

Emulation Flow Execution & Implementation

Execute end-to-end emulation flow from high-level model generation and RTL synthesis to complex system-level testing and silicon-accurate debugging
Work directly with next-generation emulation platforms (Zebu, Palladium, or Veloce) to implement cutting-edge methodologies
Maintain and evolve emulation flows to reduce compile times and increase execution speed, directly impacting time-to-market
System-Level Debug & Validation

Drive initial model bring-up process in high-stakes environment, identifying and resolving complex bugs
Ensure rapid cycles from RTL to functional stability through systematic debug approaches
Own technical blocks and drive them to completion independently
Cross-Functional Collaboration

Partner with Firmware, Software, and Validation teams to debug complex system-level scenarios
Ensure seamless hardware-software integration for AI infrastructure connectivity
Collaborate with Design and Verification teams to optimize emulation strategies

As a Senior/Staff Design Verification Engineer, you will be a key architect of quality in our Israel R&D center. You won't just run tests-you will design comprehensive verification strategies for high-performance digital blocks, IPs, subsystems, and full-chip integration. You will work at the cutting edge of AI infrastructure connectivity where "good enough" isn't an option, owning end-to-end verification plans for our most challenging designs. If you thrive on solving complex verification challenges and want to ensure the quality of chips powering the world's largest AI clusters, this is your opportunity.

Key Responsibilities

Verification Environment Architecture & Development

Design and develop comprehensive ASIC verification environments across all levels-from unit-level and subsystems to full-chip integration
Build sophisticated SystemVerilog/UVM-based testbenches including protocol/traffic generators, monitors, checkers, and functional coverage models
Own end-to-end verification plans for highly complex digital blocks, defining the "how" and "what" to ensure 100% functional coverage
Quality Assurance & Debug Excellence

Drive the debug process and leverage advanced methodologies to find critical bugs before silicon
Develop and execute comprehensive test plans to verify functionality, performance, and corner cases
Ensure verification closure through rigorous coverage analysis and assertion-based verification
Cross-Functional Collaboration & Technical Leadership

Partner with design and system architects to solve intricate hardware verification challenges
Work alongside world-class teams where knowledge sharing and technical excellence are the standard
Contribute to verification methodology improvements and automation initiatives