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we are a global leader in control systems for quantum computing, a field on the verge of exponential growth.
Our innovative hardware and software mark a groundbreaking approach in quantum computer control, scaling from individual qubits to expansive arrays of thousands.
At the core of our company lies a passionate and ambitious team committed to reshaping the construction and operation of quantum computers.
Our work is fueled by a deep understanding of customer needs, driving us to deliver unparalleled solutions in this revolutionary field.
Join our cutting-edge hardware development team as Micro-Architect and play a key role in defining and implementing the micro-architecture of advanced digital logic components.
What You'll Do:
Define and develop micro-architecture for complex logic blocks - from concept through high-quality RTL implementation
Collaborate closely with architecture, verification, design and software design teams
Write clear and detailed design specifications and drive architectural trade-off analysis
Optimize for performance and area
Contribute to innovation, methodology improvements, and technical leadership within the team.

Were building the next Gen. AI Factory, at a leading AI Infrastructure technology company. Our products sit at the core of rack-scale computing and define the performance and scale of AI systems.
If youre driven by solving problems, some dont yet have names, this is where you want to be.
In this role, you will:
Establish and lead a Back-End team with emphasis on RTL to GDS flow, Floorplan, Synthesis, Place and route, clock-tree, STA, layout, signoff (Timing, DRC, LVS) and Power
Be responsible for the Backend execution and methodologies
Be responsible to guide and lead contractors

Were building the next Gen. AI Factory, at a leading AI Infrastructure technology company. Our products sit at the core of rack-scale computing and define the performance and scale of AI systems.
If youre driven by solving problems, some dont yet have names, this is where you want to be.
About The Position:
DFT (Design For Test) is a multidisciplinary field which involves many aspects of the chip design process, including: DFT architecture definition, RTL design, verification, backend implementation, STA, pre and post production activities and many more.
You will be part of a growing team that develops from scratch its DFT implementation flow and responsible for all DFT activities and you will closely work with multiple teams within the VLSI group.

Were building the next Gen. AI Factory, at a leading AI Infrastructure technology company. Our products sit at the core of rack-scale computing and define the performance and scale of AI systems. If youre driven by solving problems, some dont yet have names, this is where you want to be.
In this role you will:
Develop and maintain all aspects of the emulation environment- Emulation model, Test plan, Validation environment
The Emulation engineer is involved in validation of significant aspects of ASIC development-chip performance, SW-HW API , system boot and functional flows
Expect to work closely and be part of the development process of the RTL design, verification, software development, testing, and more
Participate in design methodology and tool automation work as needed

Were building the next Gen. AI Factory, at a leading AI Infrastructure technology company. Our products sit at the core of rack-scale computing and define the performance and scale of AI systems.
If youre driven by solving problems, some dont yet have names, this is where you want to be.
The role includes:
Be part of a founding BackEnd team and tackle greatest technology challenges.
Responsibility for RTL2GDS flow including Floorplan, Synthesis, Place and route, clock-tree, STA, signoff (Timing, DRC, LVS, EMIR)
Take part in the definition of the Backend execution and methodologies.

Were building the next Gen. AI Factory, at a leading AI Infrastructure technology company. Our products sit at the core of rack-scale computing and define the performance and scale of AI systems.
If youre driven by solving problems, some dont yet have names, this is where you want to be.
The role Includes:
Develop ASIC verification environment for full chip, sub-cluster and unit levels. Responsibility for generation and execution of verification plan for challenging digital blocks/chip Development of System Verilog, UVM based protocol/traffic generators, monitors, checkers and coverage, Learn and work with great teammates

Were building the next Gen. AI Factory, at a leading AI Infrastructure technology company. Our products sit at the core of rack-scale computing and define the performance and scale of AI systems.
If youre driven by solving problems, some dont yet have names, this is where you want to be.
In this role, you will be:
Responsible for definition and micro-architecture of complicated digital blocks
Detailed documentation and RTL implementation including running EDA tools (Lint, CDC, simulation, debugging, synthesis and timing analysis)
Work closely with verification and architecture team
Participate in design methodology and tool automation work as needed

We are driving innovation in automotive technology, developing solutions that power the next generation of vehicles. We are looking for a Junior Engineer who is eager to learn, grow, and make an impact in a dynamic and innovative environment. This is a unique opportunity to work alongside experienced professionals, gain hands-on experience, and contribute to projects at the forefront of automotive electronics. If you are passionate about technology, curious to explore new challenges, and excited to make a real difference, we are the place to develop your skills, innovate, and grow your career.
Why join us?
* Work on cutting-edge automotive projects.
* Learn from a talented and supportive team.
* Gain exposure to real-world automotive challenges.
* Grow your career in a collaborative and inspiring environment.
If youre ready to take the next step in your career and be part of something meaningful, wed love to meet you!
About The Position:
As a Junior ASIC Design Engineer, you will take part in the full lifecycle of advanced chips that power the next generation of vehicles. This is a hands-on, growth-oriented role where youll work closely with experienced ASIC engineers, gain exposure to real silicon, and build a strong foundation in chip design and verification. In this role, you will:
* Be part of a professional ASIC team working on cutting-edge automotive solutions.
* Support and learn from real emulation platforms used in production-grade designs.
* Contribute to RTL implementation and gain practical experience in design flows.
* Assist with verification and backend (BE) activities, learning industry best practices.
* Participate in silicon bring-up, seeing your work come to life on real hardware This position is ideal for curious engineers who want to learn fast, take ownership, and grow into a key contributor in the world of automotive semiconductor design.

We are seeking a Technical Project Manager with proven expertise in High-Speed Board Design and hardware project management to join our Firewall Core Group. This role involves leading complex, cross-functional projects that combine hardware and software, driving innovation for Security Gateways.

Key Responsibilities
Lead hardware/software projects from planning through delivery.
Manage board design, hardware development, and prototype builds (EVT, DVT, PVT) with contract manufacturers.
Coordinate across R&D, QA, PMO, and Product Management teams.
Oversee software release processes and infrastructure changes.
Maintain schedules, mitigate risks, and manage external vendors.

we are looking for a Senior Formal Verification Engineer (Contractor).
This is a full-time on-site role for a Formal Verification Engineer in Petah Tikva, Israel.
The Formal Verification Engineer will be responsible for developing and implementing formal verification environments, writing and applying verification plans, and conducting formal property verification. Additional tasks include analyzing coverage results, debugging, working with design engineers to resolve issues, and reporting outcomes to ensure the accuracy and efficiency of the designs.

A problem isnt truly solved until its solved for all. Thats why Googlers build products that help create opportunities for everyone, whether down the street or across the globe. As a Technical Program Manager at Google, youll use your technical expertise to lead complex, multi-disciplinary projects from start to finish. Youll work with stakeholders to plan requirements, identify risks, manage project schedules, and communicate clearly with cross-functional partners across the company. You're equally comfortable explaining your team's analyses and recommendations to executives as you are discussing the technical tradeoffs in product development with engineers.
As a Technical Program Manager for Silicon engineering, you will use your technical and management experience to justify, plan, coordinate, and deliver custom silicon products. You will plan programs and manage their execution from early concepts through development to tapeout and production. You will collaborate closely with architecture, design, verification, physical implementation and manufacturing teams throughout the SoC execution life-cycle. This includes making technical decisions for the chip designs and methodology, driving project schedules, identifying risks and communicating them to all stakeholders, and managing partner teams.
The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers, our company Cloud customers, and billions of our company users worldwide.
We're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Justify, plan, and coordinate the delivery of custom silicon products, ensuring they meet technical specifications and business objectives.
Drive alignment and collaboration across the internal silicon ecosystem from design and verification to supply chain and quality to ensure seamless execution and operational readiness.
Lead the development of credible schedules and milestones, proactively identifying technical or timeline risks and negotiating trade offs between what is needed and what is possible.
Guide the selection, qualification, and management of external partners serving as the primary technical and program interface.
Negotiate agreements and Statement of Works (SOWs) while managing vendor performance, quality, and costs to protect the supply chain against disruptions and capacity constraints.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a SoC Physical Design Engineer, you will collaborate with functional design, Design for Testing (DFT), architecture, and packaging engineers. In this role, you will solve technical problems with innovative micro-architecture and practical logic circuits solutions, while evaluating design options with optimized performance, power, and area in mind.
The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers, our company Cloud customers, and billions of our company users worldwide.
We're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Use problem-solving and simulation techniques to ensure performance, power, and area (PPA) are within defined requirements.
Collaborate with cross-functional teams to debug failures or performance shortfalls and meet program goals in lab or simulation.
Design chips, chip-subsystems, or partitions within subsystems from synthesis through place and route, and sign off convergence, ensuring that the design meets the architecture goals of power, performance, and area.
Develop, validate, and improve Electronic Design Automation (EDA) methodology for a specialized sign off or implementation domain to enable cross-functional teams to build and deliver blocks that are correct by construction and ease convergence efforts.