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לפני 49 דקות
חברה חסויה
Location: Haifa
Job Type: Full Time
As a Q&R Lab Engineer you will help to manage the qualification and testing of some of the most advanced ICs in the world, support the maintenance of the Lab equipment and help the Q&R Engineers ensure that the AWS cloud remain the most reliable cloud in the world.


Key job responsibilities
In this role you will have end-to-end responsibility for the Q&R labs, support Annapurna's Q&R Engineers to setup and conduct reliability tests, preform tests on leading world-class ICs using high-end equipment and support the operation and maintenance of the Q&R lab.
Requirements:
Basic Qualifications
- Education - Mechanical / Electrical engineer or practical Engineer with experience.
- High technical hands-on capability with out of the box solutions.
- Experience troubleshooting and debugging technical systems.

Preferred Qualifications
- Experience with IC testing.
- Knowledge of reliability stress methods.
- Experience in writing internal work procedures and customer facing reports.
This position is open to all candidates.
 
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Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required SOC Quality and Reliability Engineer, Cloud
About the job
In this role, youll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers our most demanding AI/ML applications. Youll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
Our data centers are the most advanced in the world. In this role, you will help build the SoCs that power these data centers by driving quality and reliability processes from the integrated circuit perspective. You will create silicon and follow it into the field (and back) to drive improvements for the next generations of chips.
You will have an understanding of IC flows, wafer processing, testing, qualification, yield, reliability, and failure analysis. You will work with various cross functional teams to develop quality and reliability specifications, develop and deploy design guidelines, and develop and execute and test plans. Within the larger organization you will collaborate with global hardware quality and reliability teams, silicon design, validation and engineering teams.

Responsibilities
Drive the strategic definition and development of design-for-reliability (DfR) guidelines, collaborating with cross-functional subject matter experts to integrate reliability into early design stages.
Define and lead the development of qualification hardware and test methodologies, managing internal teams and external vendors to ensure silicon and package verification.
Execute comprehensive silicon and package qualification programs (including high-temperature operating life (HTOL), early life failure rate (ELFR), electrostatic discharge/latch-up (ESD/LU), biased highly accelerated stress test (b/HAST), etc.) and conduct failure analysis to resolve quality issues.
Extract and analyze data from qualification programs, high-volume manufacturing, and field returns to identify failure mechanisms and trends for yield and reliability optimization.
Develop and implement physics-based statistical Quality and Reliability models (e.g., ELF, time-dependent dielectric breakdown (TDDB), negative bias temperature instability (NBTI) to predict device failure mechanisms and lifetime behaviors.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Materials Science, Physics, or a related field or equivalent practical experience.
8 years of experience in IC silicon quality or reliability.
Experience leading the product reliability lifecycle from post-tapeout through high-volume manufacturing.
Experience with semiconductor complementary metal-oxide-semiconductor (CMOS) technology, device physics, and failure mechanisms.

Preferred qualifications:
Master's degree in Electrical Engineering, Materials Science, or related field.
Expertise in statistical data analysis using tools such as JMP, Python, or JSL.
Knowledge of design-for-reliability (DfR) rules and implementation techniques.
Familiarity with electrical failure analysis (EFA) and physical failure analysis (PFA) techniques.
Track record with silicon reliability on process nodes and advanced packaging technologies.
This position is open to all candidates.
 
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Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required SoC Quality and Reliability Engineer, Cloud
About the job
In this role, youll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers our most demanding AI/ML applications. Youll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
Our data centers are the most advanced in the world. In this role, you will help build the state-of-the art SoCs that power these data centers by driving quality and reliability processes from the Integrated Circuit perspective. This is an opportunity to create silicon and follow it into the field (and back!) to drive improvements for the next-generations of chips.
In this role, you will understand Integrated circuit (IC) flows, wafer processing, testing, qualification, yield, reliability, and failure analysis. You will work with various cross-functional teams to develop quality and reliability specifications, develop and deploy design guidelines, and develop and execute and test plans. Within the larger organization you will collaborate with global hardware quality and reliability teams, silicon design, validation and engineering teams.The AI and Infrastructure team is redefining whats possible. We empower customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity.
Responsibilities
Drive the strategic definition and development of Design-for-Reliability (DfR) guidelines, collaborating with cross-functional subject matter experts to integrate reliability into early design stages.
Define and lead the development of qualification hardware and test methodologies, managing internal teams and external vendors to ensure robust silicon and package verification.
Execute comprehensive silicon and package qualification programs (including HTOL, ELFR, ESD/LU, b/HAST, etc.) and conduct in-depth failure analysis to resolve quality issues.
Extract and analyze large-scale data from qualification programs, high-volume manufacturing, and field returns to identify failure mechanisms and trends for yield and reliability optimization.
Develop and implement physics-based statistical Quality and Reliability models (e.g., ELF, TDDB, NBTI) to predict device failure mechanisms and lifetime behaviors.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Materials Science, Physics, or a related field or equivalent practical experience.
8 years of experience in IC silicon quality or reliability.
Experience leading the product reliability life-cycle from post-tapeout through manufacturing.
Experience with semiconductor Complementary Metal-Oxide-Semiconductor (CMOS) technology, device physics, and failure mechanisms.
Preferred qualifications:
Master's degree in Electrical Engineering, Materials Science, or related fields.
Experience in statistical data analysis using tools such as JMP, Python, or JSL.
Familiarity with Electrical Failure Analysis (EFA) and Physical Failure Analysis (PFA) techniques.
Knowledge of Design-for-Reliability (DfR) rules and implementation techniques.
Track record with silicon reliability on process nodes and advanced packaging technologies.
This position is open to all candidates.
 
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Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required Silicon Test and DFT Engineer, Cloud
About the job
In this role, youll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers our most demanding AI/ML applications. Youll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.The AI and Infrastructure team is redefining whats possible. We empower customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity.
We're behind groundbreaking innovations, empowering the development of AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Cloud, Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Collaborate with Architecture, Design and Verification teams to develop new product bring-up, validation, characterization, and qualification strategies and manufacturing test solutions for new High Performance Computing (HPC) products in advanced process technologies.
Verify test solutions on pre-silicon models (simulation or emulation) and develop Automated Test Equipment (ATE) test modules and binning flows.
Develop and validate test programs on Automated Test Equipment (ATE) platforms for new product integration (NPI) in preparation for high-volume manufacturing (HVM), working with ATE vendors and internal cross-functional teams.
Manage product sustainment support, including analyzing volume data, improving test time and yield, assessing test escapees and return merchandise authorizations (RMAs), localizing failures, implementing containment measures, and partnering with design, manufacturing, and quality and reliability teams to identify root causes and implement corrective actions.
Build tools, flows and methodologies to continuously improve and automate the testing life-cycle.
Requirements:
Minimum qualifications:
Bachelor's degree in Engineering, Computer Science, a related field, or equivalent practical experience.
10 years of experience in test engineering.
Experience in pre-silicon validation, test content generation, automatic test equipment (ATE) program development, and post-silicon enabling from new product introduction (NPI) through high-volume manufacturing.
Experience with ASIC test methodologies (MBIST, ATPG, DFT, SerDes, and sensors).
Experience with Python, Java, C# or C/C++ and Advantest or Teradyne ATE platforms.
Preferred qualifications:
Masters in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
10 years of experience in test engineering, including product engineering.
Experience with CPU/GPU SoC architecture, design, validation and debug.
Experience in advanced testing methodologies and data analysis, including system to tester correlation, yield and test time analysis and improvement, etc.
Demonstrated expertise in developing automations for pre-silicon verification and post-silicon test-generation/test-program domains.
Inquisitive and motivated to venture into, and improve, all aspects of post-silicon testing from definition to realization.
This position is open to all candidates.
 
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09/08/2026
Location: Haifa
Job Type: Full Time
we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary System Validation Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, ensuring the reliability and testability of chips that power the world's largest AI clusters.
Job Description
The mission of this role is to perform system validation for our companys highly advanced devices, that includes defining strategy, develop tools, innovate, be creative to make sure devices are performing as they should in all aspects, logical, performance, durability, stress and more.
You will be part of the site located at Israel (Haifa - Matam), surrounded with highly experienced and professional engineers who will escort, mentor and support you on your journey at our company Labs Israel.
Requirements:
Strong academic and technical background in electrical or computer engineering
3-5 years experience validating and/or developing complex SoC/silicon products for Networking and/or Server & Storage applications
Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and work with minimal guidance and supervision.
Entrepreneurial, open-mind behavior and can-do attitude. Think and act with the customer in mind!
Required experience.
Hands-on, thorough knowledge of high-speed protocols like Ethernet CXL, PCIe, NVMe,.
Silicon/System bring-up, validation, and debug experience, including customers systems.
A Python coding experience
Familiarity with validation techniques C, C++
Experience with lab equipment as protocol analyzers, chambers, in-circuit debuggers, and CPU-based tool suites.
Familiarity with lab testing automation techniques
Preferred experience
Familiarity with devices trees and related debugging techniques.
Familiarity with board system design
C\C++ for embedded FW and device drivers
Basic understanding of x86/ARM architecture, UEFI/Linux boot sequence
Familiarity with CXL compliance standards and ability to follow and be involved in compliance consortiums to adapt the tests to be run from X86/ARM based platforms.
Experience working with DRAM memory vendors on DDR4 or DDR5 to identify issues and working on SoC HW/FW to improve memory calibration and tuning sequences.
Knowledge of memory subsystem compliance from a data integrity and RAS is a plus.
Knowledge of schematic capture and PCB layout tools from Cadence, Altium, etc.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required SOC Quality and Reliability Engineer, Cloud
About the job
In this role, youll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers our most demanding AI/ML applications. Youll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
Our data centers are the most advanced in the world. In this role, you will help build the state-of-the-art SoCs that power these data centers by driving quality and reliability processes from the Integrated Circuit perspective. You will have an opportunity to create silicon and follow it into the field and back to drive improvements for the next-generations of chips.
You will have an understanding of Integrated Circuit (IC) flows, wafer processing, testing, qualification, yield, reliability, and failure analysis is expected. You will work with various cross-functional teams to develop quality and reliability specifications, develop and deploy design guidelines, and develop and execute and test plans. You will collaborate with global hardware quality and reliability teams, silicon design, validation and engineering teams.
The AI and Infrastructure team is redefining whats possible. We empower customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity.
We're the driving force behind our groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Cloud, Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Lead the strategic definition and development of Design-for-Reliability (DfR) guidelines, collaborating with cross-functional subject matter experts to integrate reliability into early design stages.
Establish and direct the development of qualification hardware and test methodologies, managing internal teams and external vendors to ensure silicon and package verification.
Execute comprehensive silicon and package qualification programs (including high-temperature operating life (HTOL), early life failure rate (ELFR), electrostatic discharge and latch-up (ESD/LU), and biased highly accelerated stress test (b/HAST)) and conduct in-depth failure analysis to resolve quality issues.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Materials Science, Physics, or a related field or equivalent practical experience.
4 years of experience in Integrated Circuit (IC) silicon quality or reliability.
Experience leading the product reliability life-cycle from post-tapeout through high-volume manufacturing.
Experience with semiconductor complementary metal-oxide-semiconductor (CMOS) technology, device physics, and failure mechanisms.
Preferred qualifications:
Master's degree in Electrical Engineering, Materials Science, or related field.
Expertise in statistical data analysis using tools such as JMP, Python, or JMP Scripting Language (JSL).
Familiarity with electrical failure analysis (EFA) and physical failure analysis (PFA) techniques.
Knowledge of design-for-reliability (DfR) rules and implementation techniques.
Track record with silicon reliability on process nodes and advanced packaging technologies.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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חברה חסויה
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required Senior Test Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Our data centers are the most advanced in the world. In this role, you will help to manufacture the SoCs that power these data centers by developing and deploying comprehensive manufacturing test and data analytics solutions for high-volume manufacturing at wafer fabrications and Outsourced Semiconductor Assembly and Tests (OSATs). You will have an opportunity to create silicon in the most advanced technologies and follow it into the field to close the loop back to design and test for the next-generation of chips. You will help to integrate SoC technologies into devices and drive manufacturing test flows to assure performance and screen devices. You will drive yield improvement, cost optimization and work closely with cross-functional teams to ensure the optimal test coverage in production to ensure high quality SoCs. You will need to have a strong understanding of Integrated Circuit (IC) flows, wafer processing, testing, qualification, diagnostics, and failure analysis. You will work with various groups to deploy screening methodologies and flows for data processing, analytics and diagnostics. You will drive the release of cost effective production test solutions into mass production to hit yield and quality goals.
Responsibilities
Develop and implement high-volume manufacturing strategies for SoC products, optimizing ATE/SLT test coverage, reduce Defective parts per million (DPPM) and test costs, and manage product data integration.
Accelerate mass production via test program releases, data analytics, lot disposition, test time reduction, yield improvement, and return merchandise authorization (RMA) handling.
Partner with cross-functional teams (Test, Quality, Packaging, Operations) to deploy and maintain high-volume manufacturing (HVM) screening solutions.
Manage database integration for wafersort, final test, SLT, and burn-in, while overseeing test program integration, production release, binning, manufacturing flow definition, NPI material handling, and foundry process optimization.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
8 years of experience in product engineering or test engineering.
1 year of experience in people management, developing employees.
Experience with product engineering, supply chain data analytics or diagnostics for manufacturing or New Product Introduction (NPI).
Preferred qualifications:
Experience with industry standards, design tools, and design for testing (DFT) best practices, including at-speed transition delay fault (TDF), automatic test pattern generation (ATPG), memory built-in self-test (MBIST), memory repair, diagnostic tools, and yield improvement.
Experience with product engineering, supply chain data analytics and diagnostics for High Volume Manufacturing and NPI.
Experience evaluating customer returns with ATE and SLT, identifying coverage gaps, developing incremental structural and functional patterns to address quality issues, Statistical analysis (e.g., JMP), Yield Management Systems (e.g., Exensio, YieldExplorer, JMP), and Python for data analytics.
Understanding of skew lot definition, data collection, characterization, data analysis and report.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
חברה חסויה
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required SoC Test Engineer Lead, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Our data centers are the most advanced in the world. In this role, you will help to manufacture the SoCs that power these data centers by developing and deploying comprehensive manufacturing test and data analytics solutions for high volume manufacturing at wafer fabs and Outsourced Semiconductor Assembly and Tests (OSATs). You will have an opportunity to create silicon in the most advanced technologies and follow it into the field to close the loop back to design and test for the next generation of chips. You'll help to integrate SoC technologies into devices and drive manufacturing test flows to assure performance and screen devices. You will drive yield improvement, cost optimization and work closely with cross-functional teams to ensure the optimal test coverage in production to ensure high quality SoCs. You will need to have a strong understanding of IC flows, wafer processing, testing, qualification, diagnostics, and failure analysis. You will work with various groups to deploy screening methodologies and flows for data processing, analytics and diagnostics. You will drive the release of cost effective production test solutions into mass production to hit yield and quality goals.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
10 years of experience in product engineering or test engineering.
3 years of experience in people management, developing employees.
Experience with product engineering, supply chain data analytics or diagnostics for manufacturing or New Product Introduction (NPI).
Preferred qualifications:
Experience with industry standards, design tools, and DFT best practices, including at-speed TDF, ATPG, MBIST, Memory Repair, diagnostic tools, yield improvement.
Experience with product engineering, supply chain data analytics and diagnostics for High Volume Manufacturing and NPI.
Experience evaluating customer returns with ATE and SLT, identifying coverage gaps, developing incremental structural and functional patterns to address quality issues, Statistical analysis (e.g., JMP), Yield Management Systems (e.g., Exensio, YieldExplorer, JMP), and Python for data analytics.
Understanding of skew lot definition, data collection, characterization, data analysis and report.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8785661
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דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required Senior SoC Hardware Quality and Reliability Engineer
About the job
In this role, youll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers our most demanding AI/ML applications. Youll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
We're the driving force behind our groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Cloud, Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Own technical specifications, architectural definitions, and physical power-on of custom qualification vehicles (HTOL load boards, ESD fixtures, latch-up rigs). Drive external layout vendors to achieve seamless electrical correlation with ATE environments.
Govern execution quality of applied stresses, define electrical, thermal, and telemetry parameters on test vehicles to ensure uniform, valid stress profiles without unintended overstress or setup artifacts.
Lead the end-to-end engineering delivery lifecycle for qualification hardware, map and drive critical cross-functional dependencies across internal validation and product engineering teams to ensure on-time readiness.
Serve as the primary technical interface for external PCB layout houses, fabrication shops, and component suppliers; manage design reviews, track lead times, and enforce delivery schedules.
Lead laboratory troubleshooting for qualification hardware anomalies; isolate setup/socket faults from true silicon failures and drive supplier corrective actions (CAPA) when board excursions occur.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, related fields, or equivalent practical experience.
8 years of experience in hardware engineering, with a focus on authoring technical specifications, reviewing electrical layouts, and driving verification of semiconductor tests or validation platforms.
Experience driving deliverables and managing quality standards with external layout vendors, board design houses, or hardware component suppliers across multiple global geographies.
Experience working within specialized semiconductor reliability or test laboratories including configuring component Burn-In ovens, high-power stress load boards, ESD simulators, and Latch-Up test setups.
Experience managing engineering hardware delivery schedules, tracking cross-functional milestones, and meeting New Product Introduction (NPI) timelines.
Preferred qualifications:
Master's degree in Electrical Engineering, Materials Science, or related fields.
Experience managing the design execution cycle of complex multi-layer test vehicles through third-party design houses or layout vendors from concept sign-off to laboratory delivery.
Experience defining and verifying electrical correlation baselines between environmental stress setups and High-Volume Manufacturing (HVM) ATE environments.
Deep familiarity with JEDEC silicon qualification hardware standards and how they dictate physical board testing constraints.
Strong background analyzing the quality of stress factors, including power distribution networks (PDN), signal integrity degradation across extended thermal loops, and transient load behavior during reliability cycles.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8783531
סגור
שירות זה פתוח ללקוחות VIP בלבד
סגור
דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required CPU Design Verification Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will work as part of a Research and Development team. You will build verification components, constrained-random testing, and system testing, and drive verification closure. You will verify digital designs, collaborate closely with design and verification engineers on projects, and perform direct verification. You will build constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will manage the full life-cycle of verification, which can range from verification planning and test execution to collecting and closing coverage.
We're the driving team behind our groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Cloud, Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM), or formally verify designs with SystemVerilog Assertions (SVA) and industry leading formal tools.
Identify and write all types of coverage measures for corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Close coverage measures to identify verification holes and to show progress towards tape-out.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering or equivalent practical experience.
4 years of experience with creating and using verification components and environments in standard verification methodology.
Experience verifying digital logic at RTL level using SystemVerilog or Specman/E for FPGAs or ASICs.
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, or a related field.
3 years of experience creating and using verification components and environments in standard verification methodology.
Experience with Application-Specific Integrated Circuit (ASIC) standard interfaces and memory system architecture.
Experience with verification techniques, and the full verification life cycle.
Experience with performance verification of ASICs and ASIC components.
Knowledge of CPU/Processor architectures (e.g., pipeline, cache, memory subsystem, instruction sets, exceptions) like ARM, X86 or RISC-V, for verifying processor cores or IP blocks.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8782537
סגור
שירות זה פתוח ללקוחות VIP בלבד
סגור
דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required Senior SoC Design Verification Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will work as part of a Research and Development team. You will build verification components, constrained-random testing, system testing, and drive verification closure. You will verify digital designs, collaborate closely with design and verification engineers on projects, and perform direct verification. You will build constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will manage the full life-cycle of verification, which can range from verification planning, test execution, to collecting and closing coverage.
We're the driving force behind our groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Cloud, Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SVA and industry leading formal tools.
Identify and write all types of coverage measures for corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Close coverage measures to identify verification holes and to show progress towards tape-out.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering or equivalent practical experience.
8 years of experience with creating and using verification components and environments in standard verification methodology.
Experience verifying digital logic at RTL level using SystemVerilog or Specman/E for FPGAs or ASICs.
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, or a related field.
3 years of experience with creating and using verification components and environments in standard verification methodology.
Experience with verification techniques, and the full verification life cycle.
Experience with performance verification of ASICs and ASIC components.
Experience with Application-Specific Integrated Circuit (ASIC) standard interfaces and memory system architecture.
Experience in four or more System on a chip (SOC) cycles.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8783523
סגור
שירות זה פתוח ללקוחות VIP בלבד