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Required OCS Expert
About Us
An international player in construction engineering and mobility services, we offer a unique global offer combining consulting, engineering and infrastructure operation. Our capacity for innovation allows us to respond to the challenges of the climate and digital world, offering solutions and recognized expertise in the transport and mobility, sustainable city, building, water, environment and energy sectors. The Group has more than 50 years of experience, presence in more than100 countries, and over 20,000 employees around the world.
About the Role
Based in Jerusalem, you will contribute to our urban railway and LRT projects in the city, as well as future transportation projects in Israel. You will lead the OCS/OHLE engineering scope and site construction supervision, provide high-level expertise and oversee the design and implementation of OCS/OHLE systems on the LRT Blue Line.
Reporting to the Technical Manager and Project Manager, your responsibilities will include, but are not limited to:
Providing expert knowledge of Overhead Contact System (OCS) design principles in accordance with applicable international standards, incorporating lessons learned and industry best practices to support Engineering Monitoring and Consultancy (EMC) services.
Reviewing detailed design documentation, calculation notes, manufacturers submissions, and equipment approval processes prepared by the Design & Build (D&B) Contractor to ensure compliance with tender specifications, international standards, and state-of-the-art OCS/OHLE solutions.
Preparing Design Review Sheets (DRS) for submitted design documents.
Reviewing OCS designs (including foundations, poles, anchoring systems, calculation notes, contact wire leveling, tensioning systems, earthing and bonding, lightning protection, voltage-triggering devices, etc.) for both at-grade and underground tunnel sections, and recommending improvements.
Providing ongoing technical support to the clients engineering team regarding project activities.
Preparing technical queries and requests to contractors related to design, procurement, installation, testing, and commissioning-particularly at interface points with the J-Net project (existing Red Line and new Green Line).
Participating in and coordinating weekly meetings on OCS/OHLE activities, including design reviews, system integration, interface management with the existing J-Net project, and site testing supervision, involving all stakeholders (State authorities, designers, and project company).
Coordinating with other discipline experts (civil works, track, power supply, etc.) as required.
Monitoring and reporting progress to the Technical Manager and participating in regular progress review meetings.
Reviewing preliminary OCS designs for planned extensions of the Jerusalem tramway network.
Conducting site supervision visits to assess, monitor, and report on construction activities, identifying deficiencies and ensuring corrective actions are implemented by the contractor.
Representing the OCS/OHLE discipline in meetings with the client, contractors, and stakeholders as required.

Required Power Supply Expert
About the Role
Get a deep understanding and perfect knowledge of the project documentation, especially about the Power Supply system (High Voltage substations, Medium Voltage distribution network, Traction power simulation, Traction and Auxiliary substations) and the interfaced systems: Requirements (MDSM, Owner Requirements, Project Program), Interfaces & integration (NSA), and lists of Deliverables & Tasks (DTG).
Be able to verify the Design that the designers, called Line Managers (LM) will submit, to answer to their questions and to analyze their proposals.
Provide technical, and program feedback and advice on challenges, possible areas of improvement as well as possible alternatives, innovations.
Provide analyses of the LM designs and change proposals to perform Multiple Criteria Analyses to justify decisions for accepting or rejection.
Be able to decide to apply one LM proposal to the other lines for uniformity of the metro network, leading to reduce costs (for construction, integration, operation), to improve operation, make maintenance easier, or to enhance reliability, availability, and safety.
Carry out the studies to change some points of the metro tender documents and manage the LM to apply them.
Coordinate with the other technical disciplines (Rail Systems, CW, external stakeholders) for interfaces and be able to provide all required information for the success of the integration, Testing & Commissioning to get approval on power Supply and lead to the metro operation.
Serve as the Programs technical, process and professional expert on behalf of the Client, to make engineering decisions, accept design proposals or technical solutions, make recommendations, resolve technical clashes, etc., instruct and monitor the implementation and adherence to the Client Metro Network (MN) Power Supply documentation by Metro Line managers/designers and relevant Program participants.
Support, as necessary, the Client in providing technical support in relation to the management of Program statutory approval of designs.
Develop, when needed to be designed/procured at Network Level, the power Supply Programs reference design and/or performance specifications.

We are looking for a System Engineer Team Lead to lead our next generation system development.
In this role, the Project Lead will technically lead a complex multidisciplinary electro-optical system architecture. He will define and manage the required performance analysis, technical solutions, implementation methods, and field deployment to the customer's satisfaction.
Responsibilities
What you will be doing:
Technical:
Design the system architecture/high-level design and technical requirements.
Serve as the system go-to person for all technical matters; a technical expert knowledgeable in system operation, performance, and troubleshooting. Act as the technical POC for system escalations and customer support.
Project Management:
Plan, monitor, and lead the project to ensure product delivery within required specifications, on time, and within the allocated budget (Gates, PMR).
Maintain a project risk management and mitigation plan.
Lead the development activities and technical reviews throughout the PLC (SRR, PDR, CDR, FDR) and other technical design reviews.
Assign project tasks, follow up, and align with development groups, service, and production.
Lead all aspects of the beta tool delivery.
Act as the key contact for inbound topics (matrix interface) and outbound topics with MKT.
Team:
Develop and grow team ownership and technical capabilities.
Provide technical guidance for System/Product engineers.

The Production team is looking for a Production Integration Engineer to join the integrated metrology line and work on state of the art tools in the semiconductor industry.
Your role will be to manufacture the company products while maintaining highest quality and on-time delivery.
As part of your job you will interact and work with the Engineering, R&D and QA departments to solve complicated on tool problems and test new tools and features as part of the transfer to production process.
Responsibilities
What will you be doing:
Lead tool manufacturing process from start to end (1-2 weeks project).
Integration of multidisciplinary systems (optical, electronic, pneumatic, computing, and mechanical) according to predefined procedures.
Ability to solve complex system challenges, constantly learning and striving to independence.
Working with engineering and R&D to address systems/production process challenges.
Addressing quality issues and repair recommendations for suppliers by nonconformance report.
Working in an organized way using digital procedures and flow management system.
Always striving to reduce cycle time and improve working process.
Helping and consulting team members to overcome challenges on their tools.

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary DFT Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, ensuring the reliability and testability of chips that power the world's largest AI clusters.
As a DFT Engineer at our company, you will be at the intersection of architecture, design, and production. You won't just run tools-you will be a foundational member of the team responsible for the entire lifecycle of our silicon's reliability. From defining initial DFT architecture to supporting post-silicon bring-up, your work ensures that the backbone of AI infrastructure connectivity is flawless and scalable. If you thrive on solving complex challenges in deep-submicron processes and want to establish world-class DFT methodologies, this is your opportunity.
Key Responsibilities
DFT Architecture & Strategy
Be part of the DFT journey from high-level architecture definition and RTL design to backend implementation and post-production support
Develop comprehensive Design-for-Testability (DFT) strategies for next-generation connectivity platforms, ensuring chips meet the highest quality standards
Design and implement DFT architectures including JTAG/iJTAG, MBIST, Scan, and ATPG for high-end devices
Test Pattern Development & Optimization
Generate and optimize high-quality test and debug patterns for production
Perform Static Timing Analysis (STA) for DFT modes and conduct gate-level simulations to ensure robust performance
Drive test coverage and quality metrics to meet stringent manufacturing requirements
Cross-Functional Collaboration & Methodology Innovation
Act as a multidisciplinary bridge, collaborating closely with Architecture, Verification, and Backend teams to ensure seamless integration and optimal QoR
Participate in developing and maintaining cutting-edge DFT implementation flows
Automate and improve methodologies using advanced scripting and tools.

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a talented Junior ASIC Design Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful product ownership in a new site, designing the digital blocks that sit at the heart of our most ambitious connectivity projects.
As a Junior ASIC Design Engineer, you won't just build chips - you will be part of a team defining the next generation of AI infrastructure main components. The complex digital blocks under your micro-architecture and implementation responsibilities will power the world's largest AI clusters. You will own the journey from high-level definition through RTL implementation and backend support, transforming complex logic challenges into elegant, high-performance hardware. If you thrive on solving challenging problems in deep-submicron processes and want to contribute to the digital design foundation for AI infrastructure connectivity, this is your opportunity.
Key Responsibilities
Design Ownership & Implementation
Own the journey from high-level definition through micro-architecture, coding, and debug to backend implementation support
Tackle complex logic challenges and transform them into elegant, high-performance hardware solutions
Serve as the point of contact for your logic blocks, interacting with Architecture, Verification, and Backend teams
Quality Assurance & Design Optimization
Utilize industry-leading EDA tools (Lint, CDC, Synthesis, Timing, Power) and in-house quality assurance tools to ensure designs are robust, scalable, and power-efficient
Apply design techniques to meet PPA (Power, Performance, Area) targets
Contribute to design quality through verification and validation activities
Methodology Innovation & Collaboration
Participate in design methodology improvements and tool automation initiatives
Leverage AI assistance tools and contribute to in-house automation development to make engineering workflows faster and smarter
Collaborate effectively across teams to ensure seamless integration.

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a talented Junior Design Verification Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful ownership in a new site, developing the verification environments that ensure our next-generation AI silicon performs flawlessly.
As a Junior Design Verification Engineer, you will be a vital contributor to the quality and reliability of our Israel R&D center. You will work on the front lines of functional verification, developing testbenches and environments that validate high-performance digital blocks, subsystems, and full-chip designs. You will tackle complex verification challenges that ensure our connectivity solutions meet the rigorous demands of the world's largest AI clusters. If you thrive on solving technical puzzles and want to play a key role in delivering cutting-edge AI infrastructure connectivity, this is your opportunity.
Key Responsibilities
Verification Environment Development
Contribute to the design and development of ASIC verification environments, focusing on unit-level and subsystem functional blocks
Develop and maintain SystemVerilog/UVM-based components including traffic generators, monitors, and checkers to ensure robust testing
Execute detailed verification plans for challenging digital designs, ensuring all functional requirements are met and verified
Coverage & Quality Assurance
Implement functional coverage models and analyze results to identify gaps in the verification process
Drive designs toward 100% verification closure through comprehensive test development
Contribute to verification methodology improvements and best practices
Debug & Cross-Functional Collaboration
Work closely with design engineers to identify, root-cause, and resolve complex hardware bugs early in the development cycle
Apply analytical skills and debugging techniques to solve intricate verification challenges
Collaborate effectively in a fast-paced, team-oriented R&D environment.

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Junior Physical Design Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the backend execution and methodologies for chips that power the world's largest AI clusters.
As a Junior Physical Design Engineer, you will be a key architect of our silicon's physical reality. You won't just execute a flow-you will help establish our local execution culture and technical standards, owning the transformation of complex logic into high-performance silicon. You will drive the physical implementation journey from synthesis through signoff, ensuring our connectivity solutions meet the extreme performance, power, and area targets required for next-generation AI infrastructure. If you thrive on solving complex challenges in deep-submicron processes and want to shape the backend methodology for AI infrastructure connectivity, this is your opportunity.
Key Responsibilities
Physical Implementation & Execution
Be part of the founding Backend team in Israel, playing a critical role in establishing local execution culture and technical standards
Take full responsibility for physical implementation journey including Synthesis, Floorplanning, Place & Route, and Clock-Tree Synthesis (CTS)
Own macro-level implementation with deep hands-on experience in floorplanning and complex routing
Signoff & Design Integrity
Drive final stages of design integrity, owning Timing signoff (STA), Physical Verification (DRC/LVS), and Reliability analysis (EMIR)
Ensure first-pass silicon success through rigorous signoff flows and analysis
Apply Logic Equivalence Checking (LEC) and other verification techniques to guarantee design correctness
Methodology Development & Cross-Functional Collaboration
Participate in defining and refining Backend methodologies with autonomy to improve workflows and tool automation
Work closely with Architecture, Design, and DFT teams to navigate challenges of advanced process nodes and high-speed connectivity
Leverage scripting and automation to make engineering environment faster and more robust.

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we are seeking a motivated Physical Design Student to join our founding local engineering team.
This is a unique opportunity to kickstart your career in the semiconductor industry. Working alongside senior industry veterans, you will gain hands-on experience in backend execution and advanced methodologies for cutting-edge chips that power the world's largest AI clusters. If you are passionate about silicon hardware, eager to learn, and thrive on solving complex engineering challenges, this role offers the perfect bridge between your academic studies and a high-impact career.
Key Responsibilities
Guided Implementation & Learning
Partner with and learn from senior engineers to support the physical implementation journey, including synthesis, floorplanning, Place & Route (P&R), and Clock-Tree Synthesis (CTS)
Assist in macro-level implementation and develop hands-on skills in complex layout routing
Participate in deep-submicron process challenges under close professional mentorship
Signoff & Design Integrity Support
Assist in running engineering checks for design integrity, including Static Timing Analysis (STA), Physical Verification (DRC/LVS), and Reliability analysis (EMIR)
Learn to apply Logic Equivalence Checking (LEC) to help guarantee design correctness
Gain exposure to the rigorous flows required to ensure first-pass silicon success
Scripting & Cross-Functional Collaboration
Leverage and develop scripting tools to automate repetitive tasks and optimize the engineering environment
Collaborate with Architecture, Design, and DFT teams to understand how different chip design disciplines intersect
Actively participate in team reviews and technical discussions to ramp up backend methodologies.

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Principal DFT Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, ensuring the reliability and testability of chips that power the world's largest AI clusters.
As a Principal DFT Engineer, you will provide technical leadership across the full DFT lifecycle-from architecture and specification through implementation, verification, and silicon bring-up. You will define and drive DFT strategy, establish robust methodologies, and lead execution to ensure high test quality and manufacturability. This role requires deep expertise, cross-functional influence, and the ability to drive DFT excellence across projects and teams.
This is a critical leadership position with high impact on first-pass silicon success and production quality for next-generation AI connectivity solutions.
Key Responsibilities
DFT Architecture & Technical Leadership
Define and own DFT architecture for complex SoCs, including Scan, MBIST, LBIST, JTAG/iJTAG, and ATPG strategies
Lead DFT planning, specification, and quality tracking across the project lifecycle
Provide technical leadership and drive DFT sign-off readiness to ensure successful tapeout
Execution Across the Full Lifecycle
Lead DFT implementation, integration, and verification at block, full-chip and chiplet levels
Own end-to-end DFT activities from specification through silicon bring-up and production support
Ensure high test coverage, robust pattern generation, and alignment with manufacturing requirements
Methodology & Cross-Functional Impact
Develop and drive scalable DFT methodologies, flows, and automation frameworks
Collaborate closely with RTL, Physical Design, STA, and Test Engineering teams to ensure design-for-test readiness
Optimize DFT integration across front-end and backend flows to improve quality, PPA, and turnaround time.

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a talented Principal Emulation Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful ownership in a new site, implementing the emulation strategy for chips that power the world's largest AI clusters.
As an Principal Emulation Engineer, you will be a core technical driver of our Israel R&D center, working at the intersection of hardware and software to ensure our silicon meets extreme quality and performance targets. You will execute end-to-end emulation flows, bridge the gap between RTL and functional validation, and partner with cross-functional teams to enable seamless hardware-software integration. If you thrive on solving complex technical challenges and want to play a key role in validating cutting-edge AI infrastructure connectivity solutions, this is your opportunity.
Key Responsibilities
Emulation Flow Execution & Implementation
Execute end-to-end emulation flow from high-level model generation and RTL synthesis to complex system-level testing and silicon-accurate debugging
Work directly with next-generation emulation platforms (Zebu, Palladium, or Veloce) to implement cutting-edge methodologies
Maintain and evolve emulation flows to reduce compile times and increase execution speed, directly impacting time-to-market
System-Level Debug & Validation
Drive initial model bring-up process in high-stakes environment, identifying and resolving complex bugs
Ensure rapid cycles from RTL to functional stability through systematic debug approaches
Own technical blocks and drive them to completion independently
Cross-Functional Collaboration
Partner with Firmware, Software, and Validation teams to debug complex system-level scenarios
Ensure seamless hardware-software integration for AI infrastructure connectivity
Collaborate with Design and Verification teams to optimize emulation strategies.

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a talented Senior ASIC Design Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful product ownership in a new site, designing the digital blocks that sit at the heart of our most ambitious connectivity projects.
As a Senior ASIC Design Engineer, you won't just build chips-you will be part of a team defining the next generation of AI infrastructure main components. The complex digital blocks under your micro-architecture and implementation responsibilities will power the world's largest AI clusters. You will own the journey from high-level definition through RTL implementation and backend support, transforming complex logic challenges into elegant, high-performance hardware. If you thrive on solving challenging problems in deep-submicron processes and want to contribute to the digital design foundation for AI infrastructure connectivity, this is your opportunity.
Key Responsibilities
Design Ownership & Implementation
Own the journey from high-level definition through micro-architecture, coding, and debug to backend implementation support
Tackle complex logic challenges and transform them into elegant, high-performance hardware solutions
Serve as the point of contact for your logic blocks, interacting with Architecture, Verification, and Backend teams
Quality Assurance & Design Optimization
Utilize industry-leading EDA tools (Lint, CDC, Synthesis, Timing, Power) and in-house quality assurance tools to ensure designs are robust, scalable, and power-efficient
Apply design techniques to meet PPA (Power, Performance, Area) targets
Contribute to design quality through verification and validation activities
Methodology Innovation & Collaboration
Participate in design methodology improvements and tool automation initiatives
Leverage AI assistance tools and contribute to in-house automation development to make engineering workflows faster and smarter
Collaborate effectively across teams to ensure seamless integration.

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a talented Senior Design Verification Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful ownership in a new site, developing the verification environments that ensure our next-generation AI silicon performs flawlessly.
As a Senior Design Verification Engineer, you will be a vital contributor to the quality and reliability of our Israel R&D center. You will work on the front lines of functional verification, developing testbenches and environments that validate high-performance digital blocks, subsystems, and full-chip designs. You will tackle complex verification challenges that ensure our connectivity solutions meet the rigorous demands of the world's largest AI clusters. If you thrive on solving technical puzzles and want to play a key role in delivering cutting-edge AI infrastructure connectivity, this is your opportunity.
Key Responsibilities
Verification Environment Development
Contribute to the design and development of ASIC verification environments, focusing on unit-level and subsystem functional blocks
Develop and maintain SystemVerilog/UVM-based components including traffic generators, monitors, and checkers to ensure robust testing
Execute detailed verification plans for challenging digital designs, ensuring all functional requirements are met and verified
Coverage & Quality Assurance
Implement functional coverage models and analyze results to identify gaps in the verification process
Drive designs toward 100% verification closure through comprehensive test development
Contribute to verification methodology improvements and best practices
Debug & Cross-Functional Collaboration
Work closely with design engineers to identify, root-cause, and resolve complex hardware bugs early in the development cycle
Apply analytical skills and debugging techniques to solve intricate verification challenges
Collaborate effectively in a fast-paced, team-oriented R&D environment.