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Our HW team in Israel is looking for an experienced board designer to join the Hardware Switch Group. The team leads the development of networking infrastructure for our next-generation data centers focusing on accelerated performance while enabling optimized end to end GPU connectivity. We are looking for a collaborative team player, who enjoys working closely with cross-functional teams to drive innovation in networking solutions.

What you'll be doing:

Lead Pioneering Switch System design from concept to mass production.

Collaborate and integrate with all HW project fields: Board Design, Mechanics, Thermal, PCB Layout, Production, Software/Firmware, RTL and more.

Project decision maker - Technical focal point.

The position consists of product specification definitions, electrical schematics, component selection, layout guidance, hands-on testing in a lab environment, accompanying production and qualification processes.

We are looking for an experienced HPC DevOps Engineer to help us build the supercomputers and HPC clusters of the future. As a Senior HPC DevOps Engineer, you'll be a key player in groundbreaking advancements in artificial intelligence and GPU computing. Your expertise will drive the latest breakthroughs, providing insights on at-scale system design and tuning mechanisms for large-scale compute runs. You will work with the latest Accelerated computing and Deep Learning software and hardware platforms, and with many scientific researchers, developers, and customers to craft improved workflows and develop new, leading differentiated solutions. You will interact with HPC, OS, GPU compute, and systems specialist to architect, develop and bring up large scale performance platforms.

What youll be doing:

Innovate and Implement: Design, implement, and maintain large-scale HPC/AI clusters with state-of-the-art monitoring, logging, and alerting systems.

Infrastructure as Code (IaC): Utilize and develop tools to manage infrastructure as code, ensuring scalable and repeatable deployments.

Streamline CI/CD Pipelines: Develop and maintain continuous integration and continuous delivery (CI/CD) pipelines to automate and streamline deployment processes.

Automate Everything: Develop automation scripts and tools to automate deployment, configuration management, and operational monitoring.

Enhance Monitoring: Deploy advanced monitoring solutions for servers, networks, and storage to ensure seamless operations.

Troubleshoot Complex Issues: Perform comprehensive troubleshooting from bare metal to application level, ensuring system reliability and efficiency.

Lead and Educate: Serve as a technical resource, developing and sharing best practices with internal teams.

Drive Innovation: Support R&D activities and engage in proof of concepts (POCs) and proof of values (POVs) for future improvements.

We are looking for a highly qualified chip design engineer with a strong background in ASIC design to join our Chip Design Methodologies & Shared Code team. This team is responsible for developing best in class design methodologies, actively seeking for the best methods to develop design, developing shared code, providing design guidance, and driving the adoption of new technologies. It plays a key role in ensuring chip design teams operate efficiently and adhere to best practices. This role offers a great opportunity to think innovatively and make a significant impact within a dynamic, technology-focused organization.

As a Principal ASIC Design Methodologies Engineer, you will:

Develop and implement groundbreaking ASIC design methodologies that ensure flawless execution.

Drive exploration and adoption of next-generation tools, techniques, and workflows to meet the evolving demands of advanced semiconductor design.

Lead strategic initiatives aimed at redefining design practices, bringing cutting-edge methodologies to the forefront of the organization.

Collaborate with cross-functional teams to drive ambitious projects from concept to completion.

Influence and mentor other engineers, encouraging a culture of excellence and continuous improvement.

Ensure that the networking chip design team operates with maximum efficiency and the highest possible quality.

We are looking for a Senior Chip-Design Verification Engineer to join our Network Adapter Silicon group. As a Senior Verification Engineer at NVIDIA Networking Silicon team, you will join a group of passionate engineers to design and implement the next generation state-of-the-art Networking Silicon chips. In this position, you will make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!

What you'll be doing:

Work in a combined design and verification team which develops core units within the Networking silicon.

Build reference models, verify and simulate chip blocks/entities according to specifications and performance requirements.

Work closely with multiple teams within organizations such as Architecture, Micro- Architecture, FW and Post-Silicon validation.

We are looking for a top ASIC Engineer with a curiosity about SOC design automation, RTL integration, chip build and assembly, and padring design and verification. You should have real passion for methodologies and automation solutions that enable SOC creation in the most optimized way.

In this position, you will get the opportunity to build complex networking chips and interact directly with unit-level ASIC, Physical Design, CAD, Package Design, Software, DFT and other teams.

What you'll be doing:

Implement chip level design through collaboration with cross-functional teams (Functional Design, DFT, Design Verification, System Verification, STA, and Physical Design).

Be exposed and work on a variety of functional and structural challenges. Including functional debug, physical design readiness, emulation, resolve design quality issues.

Daily work involves aspects of chip level design, including partitioning, CDC, RDC, trial synthesis, design quality checks.

Taking part in flows development and deployment.