לוח משרות דרושים חשמל ואלקטרוניקה בחיפה

we are looking for a Junior Design Engineer, Google Cloud, Network
Responsibilities
Define the block level design documents such as interface protocol, block diagram, transaction flow, pipeline, and more.
Perform RTL development (e.g., coding and debug in Verilog, SystemVerilog, VHDL), function/performance simulation debug, and Lint/CDC/FV/UPF checks.
Participate in synthesis, timing/power, and field-programmable gate array/silicon bring-up.
Participate in test plan and coverage analysis of the block and SOC-level verification.
Communicate and work with multi-disciplined and multi-site teams.

we are looking for a Networking Performance Modeling Architect, Google Cloud
Responsibilities
Design, develop, test, deploy, maintain, and improve SOC software modeling and other software tools.
Manage individual project priorities, deadlines, and deliverables.
Collaborate with hardware and software architecture teams, SOC performance modeling team, and other Google software teams.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Responsibilities
Define, develop, and execute post-silicon validation content on both pre-silicon and real silicon platforms.
Drive silicon from being a chip towards becoming a product.
Debug and investigate issues along cross-functional teams such as Firmware, Software, Design, DV, - ARCH and multiple production teams.
Provide a quality functional coverage for Google designs.

we are looking for a Design Verification Engineer, CPU, Google Cloud
As a CPU Design Verification Engineer, you will work as part of a Research and Development team, and you will build verification components, constrained-random testing, system testing, and verification closure. As part of our server chip design team, you will verify digital designs. You will collaborate closely with design and verification engineers in projects and perform direct verification. You'll build efficient and effective constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will manage the full lifecycle of verification which can range from verification planning, test execution or collecting, and closing coverage.

Responsibilities
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog/UVM, or Specman.
Identify and write all types of coverage measures for stimulus and corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Lead coverage measures to identify verification holes and to show progress towards tape-out.

we are looking for a Senior Design Integration Engineer, Google Cloud, Networking
Responsibilities
Define and implement solutions for design, integration and verification problems using in-house and external technical solutions or tools. Ensure chip quality by implementing best practices and implementing quality control measures.
Participate in project development and convergence with the highest quality, and manage issues as they arise through design and implementation.
Connect between RTL design, physical design, Design for Test (DFT), external IPs and SoC while maintaining project priorities.
Maintain project infrastructure and stability.

we are looking for a Senior Formal Verification Engineer, Google Cloud
Responsibilities
Plan the formal verification strategy and create the properties and constraints for digital design blocks.
Utilize formal property verification tools combined with formal verification closure techniques to verify properties.
Resolve difficult to verify properties, and contribute improvements to methodologies to enhance formal verification results.
Architect and implement reusable formal verification components.

we are looking for a CPU Silicon Validation Lead, Google Cloud
Responsibilities
Develop and execute comprehensive validation plans for Google's custom silicon, covering functional, performance, power, and reliability aspects.
Design and build scalable validation test infrastructure, including hardware setups, software frameworks, and automation tools on Emulation or FPGA platforms.
Lead the debugging and resolution of silicon issues, collaborating with cross-functional teams such as design, architecture, software, and firmware.
Analyze validation data to identify trends, root causes, and opportunities for improvement in silicon quality and reliability.
Build and mentor a high-performing team of silicon validation engineers, fostering a culture of collaboration, innovation, and technical excellence.

we are looking for a Firmware Engineer, Networking, Google Cloud
Responsibilities
Build C/C++ firmware running on embedded processors with limited memory footprints on the SoCs.
Develop tools to update and debug the firmware, enable emulation, chip bringup, and hardware debugging.
Play key roles in Emulation, chip bring up, and SoC deployment, and contribute to all layers of the data center software stack to deploy SoCs to production.
Create code generators to generate C++ code based on hardware specifications.

As a CPU Workload Analysis Researcher within Google Cloud's MSCA organization, you will be integral to developing silicon solutions powering Google's direct-to-consumer products. You will join a Research and Development team focused on analyzing and profiling workloads requirements within the Google Cloud environment. Your role will involve conducting in-depth research on CPU optimization, feature development, and ML usages over compute platforms, contributing to identifying key areas of investment and future opportunities. This role offers a unique opportunity to perform groundbreaking research with a significant impact on both research methodologies and industry products, within the server chip architecture team. Your work will directly influence the next generation of hardware experiences for millions of Google users and Cloud customers.

Responsibilities
Plan and execute detailed analysis of CPU workloads within the Google Cloud infrastructure, analyze trends and map future requirements.
Collaborate closely with architecture and modeling owners to understand design specifications and identify critical scenarios related to CPU performance and efficiency.
Develop and implement custom workload generation tools and methodologies to simulate real-world usage patterns on Google Cloud platforms.
Analyze the impact of machine learning applications on CPU usage, identifying opportunities for optimization and feature enhancements.
Lead the investigation and development of metrics to measure CPU performance and efficiency, presenting findings to stakeholders and contributing to strategic decisions.

we are looking for a CPU Logic Design Engineer, Google Cloud, PhD, University Graduate, Start 2025
Responsibilities
Contribute to CPU frontend designs, emphasizing on microarchitecture and RTL design for the next generation CPU.
Propose performance enhancing microarchitecture features with efficiency in mind. Work with architects and performance teams for trade-off studies. Communicate pros and cons of microarchitecture enhancements. Facilitate final decision making.
Deliver designs meeting Power, performance, and area (PPA) goals with production quality.
Become familiar with techniques for at least one processor functional block. Interpret the techniques into design constructs and languages in order to provide guidance to and participate in the performance modeling effort.

As a SERDES/PCIe Silicon Validation Engineer, you will take ownership on characterization of SERDES analog IPs provided by external vendors. Your job is to assure that the IP is meeting Google high standards. You will work closely with different multi-functional teams within the Silicon organization, as well as external vendors.

Responsibilities
Perform thorough Lab characterization/Validation of Serializer/Deserializer (SERDES) IPs, such as PCIeG6 PHYs.
Write Inhouse tools/scripts to characterize the IP.
Manage bench test, debug, and characterization of analog/mixed signal on-chip circuitry (PLLs, Clocks, Data Converters and various I/O Interfaces).
Manage the development of benchtop electrical tests exercising on-chip circuitry through a combination of Joint Test Action Group (JTAG), Universal Asynchronous Receiver/Transmitter (UART), Serial Peripheral Interface (SPI), and other analog interfaces.
Draft and execute scripts to automate tests, extract results, and generate reports using database and investigative tools.

As an Executive CPU Design Verification Engineer, you will be a part of Research and Development team to verify digital designs, develop constrained-randomn test environments and drive system testing to closure. You will collaborate with design and verification teams, manage the verification life-cycle and uncover bugs through rigorous corner-case testing.
Responsibilities
Plan and execute the verification of digital design blocks by understanding specifications and working with design engineers to define key verification scenarios.
Develop and refine random verification environments using SystemVerilog/UVM or Specman to ensure effective test coverage.
Define and implement various coverage measures to capture stimulus and corner-case scenarios.
Collaborate with design engineers to debug tests and ensure functional correctness of design blocks.
Drive coverage analysis to identify verification gaps and demonstrate progress towards tape-out.

In this role, you will be part of a team developing Application-Specific Integrated Circuit (ASIC) used to accelerate networking in data centers. You will have dynamic, multi-faceted responsibilities in areas such as project definition, design, and implementation. You will participate in the design, architecture, documentation, and implementation of the next generation of data center accelerators.

You will be responsible for performance analysis for an end-to-end networking stack using your infornation of RDMA based transports.

Responsibilities
Participate in evaluation of future ASIC designs and general architecture for executing Googles data center networking roadmap: off-the-shelf components, vendor co-developments, custom designs, and chiplets.
Collaborate in developing new layer protocols for data center networking.
Understand how it interacts with software and other ASIC subsystems to implement groundbreaking data center networks.
Define performance hardware/software interfaces. Write micro architecture and design specifications.
Define efficient micro-architecture and block partitioning/interfaces and flows.