דרושים » ניהול ביניים » Analog and Power Hardware Engineer

We are looking for Analog Layout Engineer
About The Position
We are a fast-growing startup developing cutting-edge hardware infrastructure for blockchain and cloud-privacy applications.
Our team takes products from ASIC definition, planning, and implementation all the way through production and deployment in multi-ASIC operational systems.
With a multidisciplinary team boasting decades of experience in developing and manufacturing high-end ASIC products, we set the highest standards for performance, efficiency, and quality.
Roles and responsibilities:
Layout design of sensitive analog circuits where you will need to bring state-of-the-art solutions.
In close co-operation with the Circuit Designer, review and analyze complex analog schematics for layout implementation.
Ensures layout designs best functionality and quality by performing all relevant checks like parasitic checks, IR drop and Electromigration, noise and DFM.
Perform post-layout iterations to ensure the best results.

We are looking for a Electronics Board Design Engineer.
About The Position:
Development of Electronics Boards/Sub Systems for new technology projects
Development and integration of multi-disciplinary systems which includes HW/SW/Mechanics
Supporting Legacy Electronics & systems
Working according to Quality Policy, relevant Quality Procedures & Standards, and privacy & safety rules.

We are looking for an experienced Hardware Team Lead to manage our Board Design Engineering team within the AV department.
In this critical role, you will drive the development of cutting-edge automotive products by owning the design and delivery of high-performance electronic boards and systems. Your leadership will ensure projects meet the highest standards of quality, performance, and innovation.
What will your job look like?
Lead and Do: Combine strong technical leadership with hands-on hardware engineeringthis role is both strategic and actively involved in execution.
Team Management: Mentor, guide, and grow a high-performing team of hardware engineers, while setting clear technical direction and expectations.
End-to-End Project Ownership: Drive the entire hardware development lifecyclefrom architecture and schematic design to validation and release to mass production.
Design Leadership: Personally contribute and oversee electrical design, schematic reviews, component selection, and layout best practices.
Lab Engagement: Stay closely involved in board bring-up, debugging, and validationworking side by side with engineers to solve tough technical challenges.
Cross-Team Collaboration: Act as a key point of contact across software, mechanical, architecture, and manufacturing teams to ensure seamless product integration.
Customer-Facing Leadership: Represent the hardware team in technical discussions with customers, demonstrating both leadership and in-depth technical knowledge.

founded by the team that invented one of the technologies at the heart of 5G. Their next vision was to develop an IoT sticker, a computing element that can power itself by harvesting radio frequency energy, bringing connectivity and intelligence to everyday products and packaging things previously disconnected from the IoT. This revolutionary mixture of cloud and semiconductor technology is being used by some of the worlds largest consumer, retail, food, and pharmaceutical companies to change the way we make, distribute, sell, use, and recycle products.

Our investors include Softbank, Amazon, Alibaba, Verizon, NTT DoCoMo, Qualcomm, and PepsiCo.

Were seeking a highly skilled and motivated Senior Research Engineer with deep expertise in digital communication systems to join our world-class team. If you have a strong academic background, at least 5 years of relevant industry experience, and a passion for shaping the future of IoT communication technologies and standards, we want to hear from you!

Responsibilities
Drive the research and development of advanced communication technologies for ultra-low power IoT devices.
Design and evaluate algorithms for digital and wireless communication, including modulation, coding, and channel estimation.
Draft and present technical contributions in standardization bodies like IEEE, 3GPP and Bluetooth - that help shape the future of global communication standards.
Collaborate closely with cross-functional teams including systems, hardware, software, analog, and product.
Analyze technical challenges and provide innovative solutions in constrained RF and communication environments.
Stay up to date with emerging technologies and propose new research directions.

we are looking for a Senior SoC and IP Design Engineer, Google Cloud

Responsibilities
Define the SoC/Block level design document such as interface protocol, block diagram, transaction flow, pipeline etc.
Perform Register-Transfer Level (RTL) development (e.g., coding and debug in Verilog, System Verilog), function/performance simulation debug and Lint/Cyber Defense Center/Formal Verification/Unified Power Format checks.
Participate in synthesis, timing/power closure, and Application-Specific Integrated Circuit (ASIC) silicon bring-up.
Participate in test plan and coverage analysis of the block and SOC-level verification.
Participate in architecture feedback.

In this role, you will use Application-Specific Integrated Circuit (ASIC) design to be part of a team that creates the System on a Chip (SoC) design cycle from start to finish. You will collaborate with design and verification engineers in projects, creating architecture definitions with Register-Transfer Level (RTL) coding, and running block level simulations. You will contribute in ASIC designs from design specification to production. You will collaborate with members of architecture, software, verification, power, timing, synthesis and more to specify and deliver high quality SoC/RTL. You will also solve technical issues with innovative micro-architecture and practical logic solutions, and evaluate design options with performance, power, and area in mind.

Responsibilities
Own Networking Internet Protocols (IP's) Design team including definition, implementation and deployment.
Define IP development methodologies sharing unified blocks within the IP design team.
Define the block level design documents such as interface protocol, block diagram, transaction flow, pipeline, and more.
Demonstrate technical involvement throughout the entire Intellectual Property (IP) development cycle, ensuring seamless integration into System-on-Chip (SoC).
Perform RTL development (e.g., coding and debug in Verilog, SystemVerilog, VHDL), function/performance simulation debug, and Lint/CDC/FV/UPF checks.

Required Physical Design Engineer
About The Position:
We design and builds hardware that fuels disruptive blockchain technologies by accelerating compute performance. Our world-class teams are transforming the future of data, creating the infrastructure that will power the next generation of secure, scalable, green computing. The main bottleneck in scaling cutting-edge solutions in privacy tech, data analysis, and real-time computing is acceleration existing hardware cannot keep up with data processing needs. Our products reshape how data is processed and used on a global scale, and were looking for the brightest people to join us. We are seeking talented and driven individuals to become part of our Yoqneam IC team.
Responsibilities:
Floor Planning Top to Bottom & Bottom up Block level. Exploring different floorplan structures to achieve both the best area & ease of convergence.
Generate high-quality PnR results for one or more digital blocks by applying engineering best practices.
Optimize designs based on key metrics, including power, area, and performance trade-off analyses.
Drive sign-off timing convergence for high-performance designs at the block level, including DRC and LVS signoff
Analyze power integrity (EMIR) results of blocks and apply corrective measures to resolve identified issues.
Collaborating closely with frontend, verification, architecture, physical design, and analog teams.
Work closely with EDA (Electronic Design Automation) vendors on the latest tool feature development and qualification.

You will join our Cisco Silicon One team, the epicenter of Ciscos ASIC design. Our engineers handle every aspect of chip design, from definition and architecture to coding, physical design, and signoff.
Your responsibilities will include:
Spearhead innovative switch system design, guiding the process from concept through to mass production.
Collaborate with multi-functional teams in areas such as board design, mechanics, thermal, PCB layout, production, software/firmware, RTL, and more.
Act as the technical focal point and decision-maker for the project.
Conduct hands-on testing in a lab environment and support production and qualification stages.
Define product specifications, develop electrical schematics, and guide component selection and layout processes.