דרושים » הנדסה » CPU Silicon Validation Lead, Google Cloud

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Responsibilities
Define, develop, and execute post-silicon validation content on both pre-silicon and real silicon platforms.
Drive silicon from being a chip towards becoming a product.
Debug and investigate issues along cross-functional teams such as Firmware, Software, Design, DV, - ARCH and multiple production teams.
Provide a quality functional coverage for Google designs.

As a Technical Program Manager for Silicon Development, you will use your technical and management experience to lead the development and execution of complex, multidisciplinary SoC projects. You will plan programs and manage their execution from early concepts through development to tape-out and production. You will collaborate closely with architecture, design, verification, physical implementation and manufacturing teams throughout the SoC execution life cycle. This includes making technical decisions for the chip designs and methodology, driving project schedules, identifying risks and communicating them to all stakeholders, and managing partner teams.

Responsibilities
Plan, coordinate, and deliver custom silicon products.
Assess complexity and scope out the project, generate task lists, build a project timeline and work with the teams to make it into reality.
Lead the data-driven schedules and milestones, track the progress, proactively identify potential future issues, and identify mitigations with the team leaders.
Drive technical, budgetary, and schedule trade-off discussions with cross-functional teams.
Manage project execution and issues through design, development, test, manufacturing, deployment and sustaining activities for silicon and hardware products.

Our K2Core SW team is looking for a Lead System Test Engineer to define and execute the system validation strategy for the Nitro K2 card. In this technical leadership role, you will own the system-level test definition, drive cross-functional validation efforts, and ensure the end-to-end quality of our Nitro K2 card components deployed across our data centers.

This is a hands-on technical leadership role that requires expertise in embedded systems, hardware/software integration, and test automation at scale. You will work closely with HW, firmware, software, testing and platform teams across us to ensure test coverage, platform integration reliability, and production readiness.

Key job responsibilities:
Define and execute the system-level test and validation strategy for the Nitro K2 card across hardware, firmware, software and platform layers.
Lead the design and development of automated test frameworks to support scalable validation and continuous integration.
Collaborate with hardware, firmware, software, and platform teams to define validation coverage, interfaces, and testability hooks.
Own root cause analysis and debug strategy for complex, cross-subsystem integration issues originating from the production fleet.
Lead and execute hands-on system testing, and participate in the release decision process for production deployment.
Mentor and guide automation engineers, promoting a culture of system-level testing and continuous quality improvement.

we are looking for a Senior Silicon DFT Lead, Google Cloud
Responsibilities
Lead and execute DFT activities in the design, implementation, and verification solutions for Application-Specific Integrated Circuits (ASIC).
Develop DFT strategy and architecture, including hierarchical DFT, Memory Built-In Self Test (MBIST), and Automatic Test Pattern Generation (ATPG).
Work with other Engineering teams (e.g., Design, Verification, Physical Design) to ensure that DFT requirements are met and mutual dependencies are managed.
Manage a DFT team planning, deliverables, and provide technical mentoring and guidance.
Lead DFT execution of a silicon project, planning, execution, tracking, quality, and signoff.

In this role, you will help to develop and maintain emulation infrastructure, tools, and workflow methodologies supporting our Application-specific integrated circuit (ASIC) projects. You will provide emulation infrastructure and methodologies for supporting these projects. You will work with other emulation team members as well as designers, verification engineers, and software teams. You will work with with our external vendors, lab support teams, networking and security, and Electronic Design Automation (EDA) tooling and methodology teams to deliver emulation based prototyping capabilities for our ASIC projects. You will also assist in compiling projects specifying our prototyping platforms, debugging issues in both infrastructure and design, assisting in the hardware and lab bring up, and verification of our ASIC systems.

Responsibilities
Help in maintaining and upgrading emulation infrastructure and act as a primary interface to emulation vendors.
Explore emulation methodologies, gather feedback from the team, and implement emulation workflows and methodologies.
Create tooling and automation to support emulation Electronic Design Automation (EDA) tools, licensing, and job management in Google infrastructure.
Support emulation team members with debugging hardware, tooling, and project specific issues.
Help to bring up external interfaces (e.g., USB, PCIe, Ethernet, etc.) on the emulation platforms, and create standalone test cases for tool issues encountered in the emulation compile and runtime flows.

We are seeking for Platform Integration Engineer to own the development, testing, and monitoring of the manufacturing health of our Graviton server products. You will be part of a team integrating new silicon, hardware, firmware, and software into a revolutionary system architecture.

Key job responsibilities:
Lead product integration from definition phase through mass production, including: Hardware-Firmware integration and validation, development and implementation of manufacturing test flows, system validation and qualification and production readiness verification.
Define and implement screening test content for both production line and data-center environments.
Drive continuous improvement of operational health monitoring and debugging capabilities.
Collaborate with cross-functional teams to resolve integration and production issues.
Implement test flows for improving product operational health at manufacturing sites.
Integrate knowledge and data from customers and data sources for fast resolution of operational issues.
Maintain quality documentation and collateral in order to improve manufacturing operations.
Travel to manufacturing sites as needed (approximately 3-4 times per year, 1 week duration per trip) to support integration, validation, and operational improvements.

We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Develop DFT strategy and architecture (e.g., Memory Built-In Self Test (MBIST), Automatic Test Pattern Generation (ATPG), hierarchical DFT).
Complete all Test Design Rule Checks (TDRC) and design changes to fix TDRC violations to achieve high-test quality.
Insert DFT logic, boundary scan, scan chains, DFT Compression, Logic Built-In Self Test, Test Access Point (TAP) controller, clock control block, and other DFT IP blocks.
Insert and hook up MBIST logic including test collar around memories, MBIST controllers, eFuse logic, and connect to core and TAP interfaces.
Document DFT architecture, test sequences, and boot-up sequences associated with test pins.

we are looking for a Hardware Emulation Engineer, Google Cloud
Responsibilities
Help to maintain and upgrade emulation infrastructure and act as a primary interface to emulation vendors.
Explore emulation methodologies, gather feedback from the team, and implement emulation workflows and methodologies.
Create tooling and automation to support emulation Electronic Design Automation (EDA) tools, licensing, and job management in infrastructure.
Support emulation team members in debugging hardware, tooling, and project specific issues.
Help bring up external interfaces (e.g., USB, Peripheral Component Interconnect Express (PCIe), Ethernet, etc.) on the emulation platforms, and create test cases for tool issues encountered in the emulation compile and runtime flows.

We are looking for a Product & Test ATE Engineer.
The Chip Test Engineer plays a crucial role in designing, developing, and implementing automated test for IC chips and systems for Automotive industry. The Test Engineer is responsible to define and develop tests, design test features, program test scripts, and analyze test results to ensure the quality and functionality of products. The Test Engineer collaborates with cross-functional teams to troubleshoot issues, improve test processes, and support product development efforts.
Responsibilities:
Develop and implement test strategies, plans, and procedures for ATE systems to ensure comprehensive testing of ICs.
Design and develop test features, test programs, and test scripts for automated test environment (ATE) based on product specifications and requirements.
Collaborate with design engineers, product manager, production vendors and manufacturing teams to understand product functionality, performance requirements, and testability considerations.
Conduct feasibility studies and risk assessments to identify potential challenges and develop mitigation strategies for test development and implementation.
Develop test program based on code languages C++ , Java and Python.
Debug, troubleshoot, and resolve issues with ATE hardware, software, and test scripts to ensure reliable and accurate test results.
Analyze test data and results to identify trends, anomalies, and potential defects, and provide feedback to design and development teams for product improvement.
Develop and maintain documentation for test procedures, specifications, and configurations.
Collaborate with vendors and suppliers to evaluate and select ATE equipment, components, and software tools that meet project requirements and performance standards.
Stay abreast of industry trends, advancements in test technologies, and best practices in automated testing to drive continuous improvement in test processes and methodologies.

As a CPU Workload Analysis Researcher within Google Cloud's MSCA organization, you will be integral to developing silicon solutions powering Google's direct-to-consumer products. You will join a Research and Development team focused on analyzing and profiling workloads requirements within the Google Cloud environment. Your role will involve conducting in-depth research on CPU optimization, feature development, and ML usages over compute platforms, contributing to identifying key areas of investment and future opportunities. This role offers a unique opportunity to perform groundbreaking research with a significant impact on both research methodologies and industry products, within the server chip architecture team. Your work will directly influence the next generation of hardware experiences for millions of Google users and Cloud customers.

Responsibilities
Plan and execute detailed analysis of CPU workloads within the Google Cloud infrastructure, analyze trends and map future requirements.
Collaborate closely with architecture and modeling owners to understand design specifications and identify critical scenarios related to CPU performance and efficiency.
Develop and implement custom workload generation tools and methodologies to simulate real-world usage patterns on Google Cloud platforms.
Analyze the impact of machine learning applications on CPU usage, identifying opportunities for optimization and feature enhancements.
Lead the investigation and development of metrics to measure CPU performance and efficiency, presenting findings to stakeholders and contributing to strategic decisions.