לוח משרות דרושים מהנדס מחשבים משרה מלאה

What will you be doing?
Lead research, evaluation, and architectural definition of next-generation chips - from requirements through production.
Define next-generation Packet Processor / Datapath / Congestion Management architectures for high-performance, complex SoC Ethernet Switches.
Design the system architecture and detailed micro-architecture definition across major functional blocks.
Collaborate closely with design, verification, and modeling teams to ensure architectural intent is fully realized.
Work cross-functionally with other architecture teams to shape cohesive system solutions.
Explore and evaluate new technologies and innovative approaches for future products.

What will you be doing?
Envision, design and develop new features in all layers of the HPC / AI stack, from the application level, through the programming model (e.g. OpenMP, MPI) and down to the supporting libraries/middleware
Research, design and implement features for HPC / AI applications using parallel programming models (e.g. OpenMP, MPI), accelerators offloading and memory tiers.
Contribute to open-source scientific computing, networking and I/O libraries
Research, design and assist in developing hardware offloads for features relevant for scientific, deep learning, and data-intensive workloads.

What will you be doing?
Envision, design and develop new features in all layers of the HPC / AI stack, from the application level, through the programming model (e.g. OpenMP, MPI) and down to the supporting libraries/middleware
Research, design and implement features for HPC / AI applications using parallel programming models (e.g. OpenMP, MPI), accelerators offloading and memory tiers.
Contribute to open-source scientific computing, networking and I/O libraries
Research, design and assist in developing hardware offloads for features relevant for scientific, deep learning, and data-intensive workloads.

We are currently looking for a Performance Simulation Expert develop and evaluate next generation performance features as well as develop the future generation of our Compute system simulation infrastructure, models and analysis tools
Develop and analyze performance and power features in our cycle accurate pre-silicon model and improve the accuracy of the current Server system simulator
Design the architecture of the new generation system simulation platform that will be used to analyze performance of Server (Compute and AI) workloads and identify performance bottlenecks
Develop new technologies, methodologies and tools for simulation. Analysis and debug of applications and workload on Huawei servers
Propose and simulate optimizations and innovations on the HW and SW in order to improve server performance for given workloads
Distribute the simulation platform, train and support other teams in China and in Europe using the simulation platform, technology and methodology.

Looking for a CPU Architect with expertise in HW/SW codesign of dense computational logic (e.g., vector, matrix)
The role includes but is not limited to:
Analysis of technical challenges in relevant use cases and determination of whether to solve them by a combination of new HW and new SW or by only one of these
Analyzes the bottlenecks of current CPUs on workloads that reflect CPU future usage.
Invents corresponding HW features and SW solutions to address above challenges. Evaluates feasibility tradeoffs, explores, and defines new approaches and novel architectures for CPU. Develops the end-to-end architecture of new instructions in cooperation with partners. Drives the inclusion of the feature in a CPU project working with micro-architects, designers and verification experts.
(Preferably) models CPU functionality, performance and power in simulators.
Provides experimental/proof of concept changes for proposing design alternatives meeting performance, power, area, and timing constraints.
Reviews and influences cross functional roadmaps.
Collaborates with SW and HW architects, design, verification, and validation engineers during the execution of the project. Finds mitigations for issues that arise during implementation of his/her features.

The CPU Architect will take charge in defining a processor core that meets the requirement of high performance, high bandwidth, and scalable processing architecture. This architect will utilize his processor experience to deliver a world-class processor ASIC with many advanced features for Huawei products.

Our goal is to design cutting-edge CPUs for smartphones, servers, and desktops, and we need the very best talent to help us achieve it!
The CPU Architect will take charge of defining a processor on chip inter-connect and coherent fabric that meets the requirement of high performance, high bandwidth, and scalable processing architecture. This architect will utilize his processor experience to deliver a world-class processor ASIC with many advanced features for Huawei products.

In this role, you will be driving CPU architecture exploration by analyzing performance metrics (latency, power, code density) across benchmarks and CPU families. Investigate optimization opportunities through customizing ISAs and microarchitecture features to improve power and performance. You will develop simulation analysis tools and toolchain infrastructure for CPU/SOC architectures. You will collaborate closely with Apple's algorithm and software teams to build efficient CPUs, enhancing performance for diverse use cases.
Description
You will be responsible to create analysis tools to assist in architecture exploration. You will define and simulate CPU features and develop supporting tool chains including simulators, analysis tools, compiler, etc.. You will collaborate with SW and algorithm teams as well as implementation teams to define and build efficient CPUs that integrate seamlessly into various subsystems.
Responsibilities
Work with SW and algorithm teams for optimization and customization of ISAs, CPU architecture, and micro architecture features
Create and analyze benchmarks for CPU and SOC subsystem architectures
Develop architectural and performance simulators
Define and develop toolchain infrastructure

A successful, fast-growing, startup located in Raanana. We are looking for an experienced system engineer to participate and lead the development of a radio-based drone detection and mitigation system as part of the company products.
Responsibilities:
Lead features and platforms from ideas to releases.
Guide and participate in the research and analysis of both proprietary and standard radio communication protocols.
Define requirements and guide multi-disciplinary teams (SW, Algorithms, DSP, and FPGA) through implementation and debugging.
Analyze and define complex system behaviors, state machines, algorithms, and event-response logic, including radio link budget considerations.
Perform independent, hands-on debugging and optimization for system problem-solving using tools like MATLAB, Python, Excel, and other log analysis software.
Create and maintain comprehensive system-level documentation.
Gain a deep understanding of the full system to guide and support testing and validation teams, helping define methodologies, tools, and coverage strategies.

The role includes development of Automated TEST Equipment (ATE) TEST stations, including digital tests and RF tests. The engineer will be responsible for TEST system development from the requirements definition stage through delivery of the TEST system to the customer and its maintenance. The role also includes technical characterization and definition of project documents such as SPEC, SOW, TRD. Education Required: Bachelors degree in Electrical Engineering.

You'll be joining the Israeli team which is the core center of our SW and ASIC design. You'll be part of the group driving our groundbreaking next-generation network devices. Our unique team works in a startup atmosphere inside a stable and leading corporate and develops the full software stack enabling the Silicon One ASICs. Join a team of dedicated engineers with a proven track-record at delivering breakthrough products. Our R&D center is outstanding - hosting all silicon HW and SW development teams inside one site. We are transforming the industry and building a new AI/ML Networks, as well as providing a unified, programmable silicon architecture that is the foundation of all our future routing products. Our devices are crafted to be universally adaptable across service providers and web-scale markets, designed for fixed and modular platforms. Our devices deliver high speed (50+ Terabits per second) without sacrificing programmability, buffering, power efficiency, scale or feature flexibility.

We are a revolutionary, ground-breaking technology for our customers and end users for decades to come! The Internet now has a new faster, better, safer engine! You have a unique opportunity to join the core center of our SW development and work with us to design and deliver breakthrough technologies

What You'll Do:

You'll be joining our Physical Design team, which is at the center of the silicon development. Our engineers deal with all chip design aspects: definition, architecture, micro-architecture, design, verification, signoff and validation.

We use the latest silicon technologies and processes to build the largest scale and most complex devices at the edge of feasibility.

In this role, you will be part of the Switch ASIC Post-Silicon Electrical Validation (EPSV) team.
Ensure the ASIC operates according to specifications and reliably over time by performing extensive, high-precision measurements using advanced test equipment and procedures.
Conduct deep-dive investigations, integrating knowledge across hardware, software, and system domains to identify root causes of observed device behavior.

Handle all chip validation aspects, including:
Building validation plans.
Performing EPSV using advanced test and measurement equipment.
Writing tests in Python over device SDK.
Executing tests and analyzing results.

You will gain in-depth knowledge of chip architecture, functionality, and operating modes, enabling you to debug and resolve electrical chip-related issues.

Join the PHY system team, a pivotal part of our development. Our team focuses on the PHY and system aspects of our devices, including PHY firmware, calibrations, system definitions, operations, and post-silicon validation.

Key responsibilities include:

Working with the latest silicon technologies and processes to build large-scale, complex devices at the forefront of feasibility.
Contributing to the development of PHY firmware and system calibrations.
Participating in system definitions, operations, and post-silicon validation activities.

What Youll Do:

Youll be part of the group driving next-generation network devices within a startup-like atmosphere inside a well-established, leading corporation.

Our unique design center integrates all silicon hardware and software development disciplines under one roof. We are revolutionizing the industry by building a new internet for the 5G era, with a unified, programmable silicon architecture that will underpin our future routing products. Our devices are designed for adaptability across service providers and web-scale markets, delivering high speed without compromising programmability, buffering, power efficiency, scale, or feature flexibility.

We are seeking a CAD Engineer to join the Physical Design team.

You'll be joining our Physical Design team within us, which is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.

Our Backend Engineers handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.

You will be the tech lead for CAD within the team, leveraging your extensive backend and physical design experience to drive the development, optimization, and innovation of CAD methodologies and tools, ensuring the highest quality and efficiency in our chip design flows from RTL to GDS.

We demonstrate the latest silicon technologies and processes to build the largest-scale and most complex devices, pushing the boundaries of feasibility.