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Nuvoton Israel is a leading supplier of custom SoC and security hardware solutions for the computing and server markets. As a well-established and independent design center, we collaborate closely with top-tier customers such as HP, Dell, Qualcomm, Microsoft, and Google to develop advanced solutions that secure, control, and manage our customers platforms. We are seeking a talented and experienced Chip Architect to join our team. The ideal candidate is a self-motivated, fast learner with a strong background in hardware and system architecture. This role requires a technology leader capable of driving multidisciplinary programs and working closely with customers and internal teams across the entire product lifecycle. Responsibilities:
* Translate customer and marketing requirements into detailed SoC architectural specifications
* Provide functional specifications for chip hardware design and embedded software development
* Lead architectural decisions and serve as a technical authority across cross-functional teams
* Collaborate with customers and marketing to refine product requirements and align on technical solutions
* Support design, implementation, and verification processes throughout development
* Participate in system debugging, root-cause analysis, and issue resolution
* Support post-silicon bring-up, system integration, and software enablement

DRS RADA Technologies , a leading defense company developing and manufacturing life-saving radar systems, is seeking a GNC & Simulation Engineer. ?Position Overview We are seeking an analytical and hands-on GNC & Simulation Engineer to pioneer the digital foundation of our interceptor platform. In this role, you will build the "digital twin" of our aerial vehicles from scratch, simulating system-level trade-offs before physical hardware is realized. You will design, implement, and validate flight control, navigation, and terminal guidance algorithms that enable small, high-speed assets to successfully intercept dynamic targets in challenging environments. Key Responsibilities System Trade Studies: Run algorithmic simulations to analyze system-level trade-offs to support systemic architectural decisions. GNC Algorithm Design: Design and implement robust algorithms terminal guidance laws (e.g., Proportional Navigation) for dynamic interceptions. Flight Data Analysis: Post-process and analyze telemetry data from flight tests to validate, calibrate, and continuously improve the predictive accuracy of the simulation models.

We are looking for a talented V&V Manager who will build and lead the verification and validation strategy for complex defense systems, ensuring our technologies meet the highest standards of reliability, performance, and operational readiness.

What You Will Do
Hold final Go/No-Go authority for all major releases and customer deliverables, based on predefined quality thresholds and readiness criteria.
Own end-to-end V&V execution, including delivery milestones, resource planning, KPIs, and day-to-day operational performance.
Build and scale structured testing infrastructure: test plans, traceability, formal procedures, regression suites, and automation frameworks.
Increase automation coverage and reduce manual dependency through measurable quarterly improvement targets.
Lead multidisciplinary verification and validation activities, including in-house integration testing, field validation, pilot deployments, and adversarial scenario testing.
Partner with R&D to embed lifecycle quality gates and remain hands-on in system-level testing, debugging, and high-risk validation efforts during scaling phases.

Join our company as a DFT Engineer, where you will lead the design for testability (DFT) efforts to ensure optimal manufacturing and quality assurance processes for complex electronic systems.
Responsibilites
Implement DFT methodologies to improve the testability and manufacturability of electronic products and PCB assemblies.
Review schematics and PCB layouts, ensuring compliance with DFT guidelines and recommending improvements for enhanced test coverage.
Collaborate with hardware design teams to integrate DFT solutions during product development.
Perform test coverage analysis using TestWay or similar tools, define test point requirements, identify coverage gaps, and provide recommendations to development teams.
Define and maintain manufacturing test strategies, including ICT, Flying Probe, Functional Testing, and Boundary Scan (JTAG).
Develop, configure, and execute JTAG/Boundary Scan tests and create test programs for validation and production environments.
Lead test pattern generation, validation, and troubleshooting activities to ensure efficient and reliable testing.
Analyze and resolve DFT-related issues throughout development, validation, and production phases.
Define requirements for Automated Test Equipment (ATE) and support the deployment and maintenance of production test systems.
Provide technical leadership and mentorship to engineers while driving continuous improvements in testability and manufacturing processes.

DRS RADA is a global pioneer of radar systems for active military protection, counter-drone applications, critical infrastructure protection, and border surveillance. Join Our Team as a Project System Engineer at DRS RADA Technologies! DRS RADA Technologies is seeking a talented individual to join our team and contribute to the development of advanced radar-based electronic systems. About the job:
* Lead the development of advanced radar-based electronic systems
* Act as the primary point of contact for technical matters
* Collaborate with the R&D, engineering, and product teams to ensure timely delivery

As a Wireless Design Verification Engineer, you will be part of a team that is responsible for pre-silicon RTL verification of communication subsystems, SoC sub-systems and chip-level functionality. The activity may focus on block level, sub-system level or chip level, including end-to-end simulations of the entire data/control path. You will interact with DV methodologists, designers and communication systems engineers to develop reusable testbench and verification environment deploying the latest methodology with metric driven verification.

Description
- Own critical block and sub-system verification of wireless SoC projects.
- Architect and develop testbenches and environments, by using state-of-the-art verification methodologies.
- Define verification plan, create, simulate and debug test scenarios.
- Drive regression and coverage analysis to ensure high quality DV.
- Collaborate with design and systems engineering teams to review requirements, specifications and architecture, extract features and define DV attribute.

The Cellular group is seeking a highly skilled Software Engineer to join our team and develop cutting-edge Automation Infrastructure for DevOps and beyond.

In this role, you will contribute to engineering efforts from design to implementation, solving complex technical challenges in multiple areas focusing on CI/CD & SW tool development

Responsibilities
In this pivotal role, your responsibilities will include:
Design, implement, and maintain CI/CD pipelines for seamless software deployment.
SW Tools development - from idea, requirements definition, the tool's design to its implementation.
Set up infrastructure processes and methodologies to increase the groups efficiency.
Automatic deployment: control and optimize configuration management (with tools such as Ansible, Puppet, or Chef).
Monitor system performance, reliability, and scalability.
Troubleshoot infrastructure and deployment issues, ensuring high availability.
Take part in the optimisation & development of our data path solution.
Working on a varied set of platforms/technologies.

We're seeking a passionate and skilled Embedded Firmware Engineer to play a pivotal role in delivering the next generation of us. In this highly visible position, you'll be at the intersection of hardware and software, collaborating closely with logic designers to deeply understand system-level operations and performance requirements for hardware validation. In this role, you will develop critical low-level embedded firmware specifically designed to validate hardware functionality, ensure conformance, and drive performance during the bring-up and testing phases of new silicon. This involves designing, developing, and integrating complex drivers, diagnostic tests, and infrastructure essential for SoC bring-up, post-silicon validation, and debugging activities. Ultimately, you'll lead hands-on firmware development, system-level validation, and problem-solving at the hardware-software interface in a dynamic, collaborative environment, with your work directly enabling the successful launch of future products by ensuring our silicon meets the highest standards.

As member of the DV CAD team, you have the opportunity to impact our engineers who develop next generation of our products!
You will be responsible for developing software solutions used by thousands of DV engineers globally. You will be supporting design process of all chip families we make (iPhone, iPad, Mac, our Watch and more), and your work will help streamline this complex process. This role combines DV knowledge alongside modern software engineering practices. Your work will be very diverse, and you will have broad impact contributing to the success of us.


You will develop and drive software development of multiple tools across the DV space, including cloud-native services, GUI, LLM harness, CI/CD. Your work will span from software development and architecture to collaborating with DV engineers, working with EDA vendors, and supporting critical project milestones.

Responsibilities
Developing and maintaining LLM harness for agentic DV workflows, and being responsible for benchmarking and improving accuracy of agentic workflows.
Building and managing cloud-native services running on k8s, including CI/CD, containerization, alerting, databases, GUI and monitoring.
Communication with DV stakeholders and working to understand user requirements.
Writing and maintaining Python scripts used as part of design simulation flows.
Supporting multiple projects simultaneously.

We are looking for a CAD/Emulation Engineer to join our infrastructure team. This position is providing hands-on experience with advanced VLSI CAD/Emulation flows and infrastructure.
Key Responsibilities
Develop and maintain automation scripts for front-end Emulation and VLSI CAD flows and automation.
Support execution and releases of VLSI artifacts while maintaining advanced CAD flows.
Assist in improving infrastructure efficiency and tool integration.
Work with advanced version control systems and CI/CD pipelines for regression and build environments
Responsible for top notch emulation methodologies and procedures.

Required Physical Design Engineer, SoC Static Timing Analysis
About the job
In this role, youll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers our most demanding AI/ML applications. Youll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. In this role, you will contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering exceptional performance, efficiency, and integration.
Responsibilities
Drive the sign-off timing convergence for high-performance designs.
Set up the timing constraints, define the overall static timing analysis (STA) methodology, set up the STA infrastructure and sign-off convergence flows, and work closely with block owners throughout the project for sign-off timing convergence.
Work with logic designers to drive architectural feasibility studies, develop timing, and explore RTL/design trade-offs for physical design closure.

Physical Design Lead, Cloud
About the job
In this role, youll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers our most demanding AI/ML applications. Youll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
In this role, youll work to shape the future of an Edge-AI product, bringing high-performance intelligence to the edge. You will have an opportunity to drive distributed inference technology that powers real-time systems where latency and reliability are mission-critical.
Youll be part of a team that pushes boundaries, developing, autonomous solutions that define the next generation of intelligent infrastructure and hardware for the edge. You'll contribute to the innovation behind products that transform industries, leveraging your expertise in system-level integration and localized processing to deploy complex AI models across sophisticated hardware platforms, ensuring intelligence is embedded exactly where the action happens.
Responsibilities
Lead physical design of complex SoC to tape-out while working with multiple team members.
Evaluate and develop physical design methodologies and decide on the SoC flow.
Work with architects and logic designers to drive architectural feasibility studies, develop timing, power and area design goals, and explore RTL/design tradeoffs for physical design closure.
articipate in design reviews and track issue resolution, and engage in technical and schedule tradeoff discussions. Create execution plans for projects and manage team efforts from concept to working silicon in volume.
Understand architecture and design specifications with the larger team, and define physical design strategies and tactics to meet quality and schedule goals.

Required Design Team Manager, Servers, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a Design Team Manager within the Server Chip Design team, you will use your ASIC design experience to be part of a team that creates the SoC VLSI design cycle from start to finish. You will collaborate closely with design and verification engineers in active projects, creating architecture definitions with RTL coding, and running block level simulations.
In this role, you will oversee the Intellectual Property (IP) and SoC VLSI design cycle from architecture to production. You will own and manage IP, subsystems and SoC development, leading a group of designers and design tech leads. You will be responsible for mentoring and developing team members and tech leads, driving improvements in leadership, technical execution, and design flows.
Responsibilities
Manage a team of tech leads and designers. Develop and mentor team members, and communicate and co-work with multi-disciplined and multi-site teams.
Lead design activities at IPs, subsystems, and System-on-Chips (SoCs).
Plan, execute, track progress, assure quality, and report status of the assigned activity.
Work closely with internal customers and support multiple activities and deliverables.
Assure and manage deliverables quality at all RTL design categories including reviews, static checks, design for physical design, power, etc.

Required Senior RTL Design Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will use Application-Specific Integrated Circuit (ASIC) design to be part of a team that creates the System on a Chip (SoC) design cycle from start to finish. You will collaborate with design and verification engineers in projects, creating architecture definitions with Register-Transfer Level (RTL) coding, and running block level simulations. You will contribute in ASIC designs from design specification to production. You will collaborate with members of architecture, software, verification, power, timing, synthesis and more to specify and deliver high quality SoC/RTL. You will also solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with performance, power, and area in mind.Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of our platforms, we make our product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
Lead a complex ASIC subsystem.
Understand how the subsystem interacts with software and other ASIC subsystems to implement groundbreaking data center.
Define high-performance hardware/software interfaces. Write micro architecture and design specifications.
Define efficient micro-architecture and block partitioning/interfaces and flows.
Collaborate closely with software, verification, and physical design stakeholders to ensure the designs are complete, correct, and performant.