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we are looking for an experienced PHY/Radio Validation Engineer to join our System Validation & Compliance team. He will play a key role in validating an Automotive communication system that will be deployed in millions of vehicles. He'll be part of the Engineering team working on validation and compliance of wireless communication standards for our company next generation communication SoCs.
About The Role
PHY/Radio Validation Engineer will take part in achieving the compliance milestones and shape the infrastructure needed for that. The compliance is defined according to the various wireless standards supported in our company cutting edge chipsets, augmented by internal requirements.
The position includes deep diving into system and standard requirements, having end to end responsibility for planning and implementing the tests and analyzing the results, working closely and collaboratively with other development teams.
This is a 5 days onsite position in Kfar-Netter
Responsibilities
Analysis of the standards & relevant system requirements to create compliance test plans.
Definition of detailed test-plans to cover the Radio system functional, performance and compliance requirements including participation in requirement, design and leading test plan reviews.
Definition and routine management of test infrastructure including required test equipment, test setups, and automation code to carry out the tests.
Integration and verification of automation infrastructure.
Implementation & execution of compliance test suites as well as creation of compliance reports.

We are looking for a Formal Verification expert specializing in RTL/ASIC verification to work on a new cutting-edge RISC‑V application processor. The role involves ownership of formal methodologies, verification strategy definition, and close collaboration with architecture and design teams to ensure full functional correctness of complex processor units.
An ideal candidate will have at least 8 years of work experience with various formal applications and tools.
This is a 5 days onsite position in Hod Hasharon
Responsibilities
Understand high-level specifications and detailed requirements for application processor design logical units.
Collaborate with cross functional teams such as architecture, design, and software teams on formal verification planning.
Formal Verification expert to lead all formal activities for a new RISC-V application processor.

As an RTL Verification Engineer, you will be responsible for complex logical units of a new, cutting-edge RISC‑V application processor, working closely with architecture, design, modeling, software, validation, and implementation teams to meet all functional requirements, including performance, power, and area (PPA) goals.
An ideal candidate will have at least 3 years of experience in one or more of the following: CPU, RISC‑V architecture, micro‑controllers, and memory or cache controller design verification.
This is a 5 days onsite position in Hod Hasharon
Responsibilities
Understand high-level specifications and detailed requirements for application processor design logical units.
Verification from plan to execution, build and own all functional verification stages of a unit within application processor.
Collaborate with cross functional teams such as architecture, design, and software teams on test plan development.
Deliver on time with tight schedule entire verification suite including full functional and code coverage closure before tape-out.

We are now looking for a Senior Chip Design Verification Engineer to join our Switch Silicon team.As a Chip Design Engineer at NVIDIA's Networking business unit, you'll join a group of passionate engineers to design and implement the next generation state-of-the-art Switch Silicon chips. In this position, you'll make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!

What You'll Be Doing:
Work in a design/verification team which develops core units within the Switch silicon.
Micro-architecture of dynamic verification environments planning for units and modules.
Design dynamic verification environments of units/blocks according to Arch. specifications under challenging constraints with high orientation to power, area, and performance.
Work closely with multiple teams within organizations such as Architecture, u-arch, Full chip Micro-Architecture, BE, and FW.

Join our Networking Silicon team as a Senior Full-Chip Design Verification Engineer. In this role, you will be responsible for the development and verification of our next-generation NICs at the system level. You will contribute to the architecture of high-speed communication devices by building advanced simulation platforms and driving full-chip verification execution for the networking solutions powering the worlds most advanced data centers.

What youll be doing:

Full-Chip Verification & Execution: Own complex system-level features by defining verification plans and driving the end-to-end execution.

Software Simulation Development: Architect and code robust software simulation platforms that serve as the foundation for Firmware development and uArchitectural research.

AI-Enhanced Engineering: Accelerate development by leveraging cutting-edge AI coding tools and frameworks.

Global Technical Collaboration: Partner with Architecture, FW, and SW engineering teams across the globe to deliver industry-leading networking solutions.

What you'll be doing:

Test Verification and Validation (both HW and SW).

Maintain products quality by improving test stability, coverage, design, and manufacturing process in Mass Production.

Execute tests in different scopes such: as regression, performance degradation, functional, and security; report the progress of testing and provide summary reports of the activity.

Troubleshooting and streamlining/optimizing our testing procedures.

Support Mass production matters.

Debugging production bugs and solving them.

We are now looking for a best-in-class Verification Engineer to join our outstanding GPU-Networking Silicon Engineering team. As a DV Engineer in our GPU-Networking group, you'll make a real impact in a dynamic, technology-focused company while being a part of the team that develops the flagship product of todays semiconductor industry - our GPU Super-Chip.

What youll be doing:

Work in a DV (Design Verification) team that has a global responsibility over deliverable units and clusters to the silicon GPU.

Integrations and Full-Chip models.

Verification of chip blocks/entities according to specifications under challenging constraints.

Ramp-up and run DV tasks on emulation platform.

we are a game-changing startup that's giving advanced electronics the power to report on their own health. In a digital world built for autonomous driving, cloud computing, and AI, we depend on computing systems daily. But how can we guarantee their safety, reliability and functionality? we are the first-ever company to provide visibility into next-gen chips while they are operating, based on the power of on-chip monitoring, machine learning, and data analytics.
Here at our company, you'll be part of a team that's unlocking deep insights to make electronics more reliable, efficient, and high-quality. We're trusted by industry leaders in data centers, automotive, communications, and consumer devices - we work with the world's largest and most notable companies in tech.
Responsibilities
Develop and maintain advanced verification environments using SystemVerilog and UVM, ensuring scalability, configurability, and reusability across multiple IPs.
Design, implement, and execute comprehensive testbenches and random test suites to validate functional correctness, robustness, and corner-case behavior of complex IP within various SoC integration environments.
Drive coverage closure by defining, collecting, and analyzing code and functional coverage metrics; identify verification gaps and ensure complete validation of feature sets prior to sign-off.
Lead debug and root-cause analysis efforts in collaboration with senior verification and design engineers, leveraging carefully crafted logs, waveform analysis and assertions to isolate and resolve design or environment issues.
Collaborate closely with architecture, design, and firmware teams to ensure verification completeness, alignment with design intent, and seamless integration at the system level.
Contribute to methodology and infrastructure improvements, including reusable UVM components, automation scripts, and best practices that enhance team efficiency and verification quality.

We are seeking a dynamic and professional product engineer (PE), who enjoys multi-tasking in a fast paced, technical, and friendly environment. In this position you will be focused on product and deployment scalability of the Questa One Formal products with a specific focus on Verify Property quality, performance, and deployment. As a PE you will be working closely with product development teams, marketing managers, application engineers and customers. Some domestic and international travel will be required.
Product Engineers define product features and methodologies:
In this role you will be defining feature and product requirements for the formal products to address current and emerging design challenges. You will be working closely with product development and marketing teams to connect these challenges with our companys current and emerging technical solutions. You will also be guiding customers on formal methodologies and optimizing usage within customer environments.
Support marketing activities:
The PE will work closely with marketing teams to perform market research, product positioning and create supporting presentation materials. You will present and demonstrate the Questa One Formal products in conferences, seminars and events.
Work with customers:
You will be working with individual customers to understand their challenges and support methodology improvements to drive best in class solutions. Your ability to maintain customer relationships will help make you effective in this role. Customer-facing activities include product demonstrations, training, deployments, and competitive benchmarking. PE plays an active role in developing solutions to solve customer problems based on their insight into the customers environment.
Ideally, you will be a seasoned Formal Property Verification (FPV) expert who has knowledge of RTL design needs and formal verification methodologies. Additional responsibilities include:
Identifying market and customer profiles to deploy formal methodologies and technologies. Developing a network of technical relationships at a peer-to-peer level with both our customers and the product engineering teams.
Delivering technical presentations, demonstrations and training to a range of audiences including users, managers, and decision-makers.
Influencing product direction by gathering customer requirements and defining the use of models which drive product development and marketing teams.
Participating in new feature specification, development, and validation processes to ensure the solution will meet customer requirements.

We are looking for a highly motivated and experienced Senior Verification Engineer to perform and guide design verification for the electro-mechanical portions of the system design.
For this role, were focusing on electrical and mechanical parts, assembly and functional aspects of the system design. This is an ideal opportunity for someone who is motivated and passionate to make an impact in leading the development of the next generation of ophthalmic robotic surgery.
Responsibilities
Create verification protocols based on electromechanical design input requirements.
Identify applicable standards for each electromechanical aspect and define how they are addressed in verification activities.
Establish statistical sample sizes according to the risk level associated with each part, assembly, and feature.
Lead protocol development and test execution for sterilization validation.
Guide a team of verification engineers and testers in creating test protocols, executing tests, reviewing results, and generating reports.
Participate as a team member in the development of new features related to electromechanical assemblies and associated robotic capabilities.

We are looking for a talented and experienced engineer to take part in the verification efforts for the companys core product. This position involves building and maintaining a complex verification environment, and defining and executing a test plan. In this role, you will be leading all aspects of verification and will have a critical impact on the company's R&D path.
Responsibilities
Define and implement robust SV/UVM verification solutions, including test benches and methodologies, to drive efficient verification closure across block-level and full-chip designs, integrating Mix-signals SoC simulation environment using Verilog, MATLAB, HW/SW Co-simulation and lab integration.
Work closely with Digital Design, Analog Design, Software, Back-end, SW and System teams to understand the functional, power and performance goals of the product and ensure its quality.

We are looking for a talented and experienced engineer to take part in the verification efforts for the companys core product. This position involves building and maintaining a complex verification environment, and defining and executing a test plan. In this role, you will be leading all aspects of verification and will have a critical impact on the company's R&D path.
Responsibilities
Lead the full verification lifecycle and methodologies. Plan, Design and Execute verification of SV/UVM Block level and Full chip environments , creating and execution test plans, tracking progress, and ensuring verification closure across diverse Mix-signals SoC simulation using Verilog, MATLAB, HW/SW Co-simulation and lab integration.
Work closely with Digital Design, Analog Design, Software, Back-end, SW and System teams to understand the functional, power and performance goals of the product and ensure its quality.

We are seeking a Signal Processing Lab and Development Validation Lead to establish a new team in a classified, cutting-edge technological environment. This is a key role in projects that directly contribute to national security.
Position Description
Manage and operate four advanced laboratories specializing in RF and signal processing
Design, set up, and execute complex test environments and validation processes
Analyze test results and identify issues in collaboration with development teams
Oversee lab infrastructure including equipment, computing systems, and procurement
Work closely with suppliers, internal systems, and external partners
Operate diverse test and measurement equipment (oscilloscope, spectrum analyzer, etc.).

Were hiring an experienced verification engineer to join our team developing advanced telecommunications ASIC/FPGA products.
You will join family, as part of our team in Beer-Sheva.
Responsibilities:
Build and maintain verification environments (SystemVerilog/UVM or Specman)
Develop test plans and run constrained-random & directed tests
Debug, analyze coverage, and work closely with design teams
Contribute to methodology and process improvements