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we are seeking for a Verification engineer. We are seeking a highly skilled Verification engineer to join a Processor Verification team working on nextgeneration processor cores. In this role, you will take a key part in verifying critical processor blocks, collaborating closely with architecture and design teams to ensure functional correctness. You will own verification activities endtoend from TEST planning and environment development to execution, coverage analysis, and closure- using advanced verification methodologies.

We are looking for a hands-on ETH SerDes Validation Engineer to lead and execute 112G and next-generation 224G SerDes validation activities.
The role involves deep lab work with Keysight test equipment, automation development, and direct execution of compliance and characterization tests according to industry standards.
This position is ideal for an engineer who combines strong signal-integrity fundamentals, standards expertise, and automation-driven validation in high-speed silicon and system environments.
Key Responsibilities
Perform end-to-end validation of 112G / 224G SerDes PHYs at silicon, package, and system levels
Execute compliance, characterization, and stress tests for high-speed serial links
Operate and configure Keysight high-speed test equipment, including:
BERTs, oscilloscopes, AWGs, jitter sources, channel emulators (variable ISI)
Develop and maintain automation frameworks for SerDes validation:
Test setup control
Data collection
Result analysis and reporting
Python
Shell scripts under Ubuntu
SQL skills for data analysis
Execute and analyze:
Eye diagrams, jitter (RJ/DJ/TJ), BER, bathtub curves
CTLE/DFE behavior
TX FIR optimization
Channel loss and margin analysis
Debug signal-integrity issues across:
Silicon
Package
PCB
Connectors and cables
Work according to industry standards, including:
IEEE (112G / 224G PAM4)
Ethernet (802.3ck / 802.3db and beyond)
Collaborate closely with:
Design teams (SerDes / PHY)
SI/PI engineers
System and board design teams
Document test methodologies, results, and recommendations clearly.

We are looking for a brilliant Verification engineer that can quickly join a most promising and exciting startup company to take a part in and contribute in developing a complex and challenging chip for the data center.
Culture and atmosphere of the company are top innovative, technically challenging, and super pleasant.
Required Experience:
0-2 years of chip design development
Brilliant new graduates with an average above 85, are also welcome to apply for this position.
Experience in logic design, verification, and debug - advantage
Knowledgeable in frontend design tools - advantage.

We are looking for an experienced and highly skilled Verification Engineer to join a fast-growing and exciting startup in the data-center domain.
You will play a key role in the verification of a complex, high-performance chip, working on challenging problems, influencing methodology, and helping drive quality and efficiency across the project.
Why Join Us?
Work on cutting-edge silicon for data-center applications
High technical bar with real ownership and impact
Opportunity to influence verification architecture and methodology
Collaborative, friendly, and innovation-driven culture.

As a Wireless Design Verification Engineer, you will be part of a team that is responsible for pre-silicon RTL verification of communication subsystems, SoC sub-systems and chip-level functionality. The activity may focus on block level, sub-system level or chip level, including end-to-end simulations of the entire data/control path. You will interact with DV methodologists, designers and communication systems engineers to develop reusable testbench and verification environment deploying the latest methodology with metric driven verification.
Description
- Own critical block and sub-system verification of wireless SoC projects
- Architect and develop testbenches and environments, by using state-of-the-art verification methodologies
- Define verification plan, create, simulate and debug test scenarios
- Drive regression and coverage analysis to ensure high quality DV
- Collaborate with design and systems engineering teams to review requirements, specifications and architecture, extract features and define DV attribute

As a Design Verification Manager for the IP Group, you will lead a focused team responsible for the quality and reliability of our critical IP blocks. You will steer the IP verification roadmap, oversee the development of complex testbenches, and ensure our next-generation AI silicon meets the highest standards. Leading a team of talented engineers, you will tackle challenges at the unit and sub-system levels, playing a pivotal role in delivering high-performance hardware for the worlds largest AI clusters.

Key Responsibilities



Lead and mentor a team of design verification engineers, defining the technical roadmap and methodology for ASIC verification across unit and IP/sub-system levels
Drive the creation and execution of comprehensive design verification plans, ensuring all functional requirements are met on schedule for complex digital IPs
Oversee the architecture and maintenance of block-level verification strategies, heavily utilizing SV-UVM, alongside Formal Verification where applicable
Define functional coverage goals and quality metrics, driving the IP team toward 100% verification closure and sign-off
Partner closely with IP Design and Architecture teams to align on specifications, root-cause complex bugs, and optimize the IP development cycle

As a Senior/Staff Design Verification Engineer, you will be a key architect of quality in our Israel R&D center. You won't just run tests-you will design comprehensive verification strategies for high-performance digital blocks, IPs, subsystems, and full-chip integration. You will work at the cutting edge of AI infrastructure connectivity where "good enough" isn't an option, owning end-to-end verification plans for our most challenging designs. If you thrive on solving complex verification challenges and want to ensure the quality of chips powering the world's largest AI clusters, this is your opportunity.

Key Responsibilities

Verification Environment Architecture & Development

Design and develop comprehensive ASIC verification environments across all levels-from unit-level and subsystems to full-chip integration
Build sophisticated SystemVerilog/UVM-based testbenches including protocol/traffic generators, monitors, checkers, and functional coverage models
Own end-to-end verification plans for highly complex digital blocks, defining the "how" and "what" to ensure 100% functional coverage
Quality Assurance & Debug Excellence

Drive the debug process and leverage advanced methodologies to find critical bugs before silicon
Develop and execute comprehensive test plans to verify functionality, performance, and corner cases
Ensure verification closure through rigorous coverage analysis and assertion-based verification
Cross-Functional Collaboration & Technical Leadership

Partner with design and system architects to solve intricate hardware verification challenges
Work alongside world-class teams where knowledge sharing and technical excellence are the standard
Contribute to verification methodology improvements and automation initiatives

we're seeking a visionary Formal Verification Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the formal verification strategy for chips that power the world's largest AI clusters.

As the Formal Verification Engineer, you will be a foundational member of our Israel R&D center. You wont just execute tasks; you will define the Formal verification strategy for chips that drive the worlds largest AI clusters. You will dive deep into the technical details, proving the correctness of complex designs and ensuring they flawlessly meet specifications.

Key Responsibilities

Own and develop formal verification environments from scratch through to sign-off
Apply formal verification methodologies and strategies to prove the correctness of intricate designs
Work closely with the Architecture, Design, and DV teams to identify verification needs and pinpoint design requirements
Create robust formal environments, analyze complex RTL designs, and apply advanced formal techniques to find corner-case bugs
Analyze verification results, identify failures, and collaborate directly with designers to resolve issues efficiently
Architect and develop generic, common formal functions and properties to be reused across multiple projects

We are seeking a Signal Processing Lab and Development Validation Lead to establish a new team in a classified, cutting-edge technological environment. This is a key role in projects that directly contribute to national security.
Position Description:
Manage and operate four advanced laboratories specializing in RF and signal processing
Design, set up, and execute complex test environments and validation processes
Analyze test results and identify issues in collaboration with development teams
Oversee lab infrastructure including equipment, computing systems, and procurement
Work closely with suppliers, internal systems, and external partners
Operate diverse test and measurement equipment (oscilloscope, spectrum analyzer, etc.).

Required V&V Engineer
Location:
Afek Industrial Park, Rosh HaAyin
Reports to:
DTG Manager (QA)
V&V Engineer ensures that our products meet all system requirements, adhere to specifications, and deliver a high-quality, competitive solution that fulfills customer needs and expectations.
What will you do?
Serve as the Verification & Validation focal point
for a dedicated program within an Agile team.Conduct requirements and PBI analysis , as well as risk assessment and comprehensive test planning.
Design and execute tests at all levels - from software standalone to full system integration, including black box and grey box testing at the system level.
Define and develop automated tests to support both V&V and R&D activities.
Analyze, document, and report test results , ensuring accurate defect logging and tracking to resolution.
Monitor and follow up on defects and open issues through their full lifecycle.
Collaborate with development teams to provide actionable feedback, support fault isolation, and maintain high-quality data handoffs.
Identify and investigate cross-product issues and dependencies.
Support the Service and Field teams in resolving escalated customer issues and contributing to root cause analysis.

Review micro-architecture specifications

Supervise verification team members and provide professional guidance

Implement Verification environment UVM based

Collaborate with Design engineers to resolve bugs and achieve coverage closure

Work with the firmware/Lab teams to verify chip flows

Perform debug, root-cause analysis, and post-silicon validation in the lab

Develop advanced verification environments using SystemVerilog and UVM
Write, run, and debug testbenches to ensure complete functional coverage
Drive pre-silicon and in-lab debug activities to resolve complex issues
Collaborate with RTL, architecture, and physical design teams to achieve design closure
Support methodology development, scripting, and automation to enhance productivity

Develop advanced verification environments using SystemVerilog and UVM
Write, run, and debug testbenches to ensure complete functional coverage
Drive pre-silicon and in-lab debug activities to resolve complex issues
Collaborate with RTL, architecture, and physical design teams to achieve design closure
Support methodology development, scripting, and automation to enhance productivity
Contribute to the success, powering the next generation of Internet infrastructure

In this role, you will be part of the Silicon One Switch ASIC Post-Silicon Electrical Validation (EPSV) team.
* Ensure the ASIC operates according to specifications and reliably over time by performing extensive, high-precision measurements using advanced test equipment and procedures.
* Conduct deep-dive investigations, integrating knowledge across hardware, software, and system domains to identify root causes of observed device behavior.

* Handle all chip validation aspects, including:
* Building validation plans.
* Deloping ASIC software test infrastructure.
* Writing tests in Python/C++ over device SDK.
* Executing tests and analyzing results.