our companys Product Engineering group is looking for a well experienced Test architect to join our family and be a part of System Product Engineering. The System Product Engineering team is responsible to assure that our companys customers will get the best state of the art high-quality products.
The teams are involving and part of the full product lifecycle from architecture definition trough development till the product will be EOL (end of life). As part of the effort mentioned above, we are looking for an Electronic Engineer to join the System Design Testing Architecture team and lead Systems HW testability definition for our companys Networking systems.
What youll be doing:
Leading optimal products testing definitions includes: HW, SW, FW, Mechanical fixtures, and cables/harnesses for customized production testing set ups.
Making pitches in front of large audience a new product testing architecture, DFT and testing method while providing justifications for the testing concept.
Responsible for product testing maximum coverage, Testing specification documents and production test flow process for each system
Working with Companys engineering team during the developing process of the product from pre-design trough the design and influence on the product design from DFT design for testability aspects.
Supporting production ramp up and scalability, lead and fast responding time for ECR/ECO implications.
Examine New Technologies, testing capabilities and their implementation for the next generation products
Ensure testing set ups and coverage are met the DFT requirements and timetable
Lead DFT Risk assessment and drive mitigations to reduce the risks.
Working closely with variety of teams: R&D, HW and SW, Chip design, Operations, thermal, signal integrity, FW and SW, layout, and more
The position combines understanding of HW, SW, system manufacturing processes.
Requirements: BSc, MSc Electrical Engineering (or equivalent)
Integration capabilities of self-task management, vast electronic knowledge, production and testing process knowhow.
Background in working with contract manufacturers and suppliers
Solid understanding of signal integrity concepts and their implications on DFT and high-speed testing.
Familiarity with SERDES architecture and high-speed interface testing.
Minimum 5 years of experience as a DFT engineer at chip/system level, as Board Design engineer or as system architect
Management and follow up till completion of multi-functional and personal tasks.
Personal skills: proactive and self-instruction, good interpersonal relationship, multitasking, well organized and a quick learner.
This position is open to all candidates.