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Biz Dev & Sales Director - Latin America Job Description We are seeking an experienced Business Development & Sales professional with a strong background in international markets and the defense and security industry. The role is responsible for managing the full business development and sales cycle within assigned territories - from identifying and developing new business opportunities, through establishing and managing relationships with clients and partners, to contract negotiations, closing, delivery, and follow-on sales. The position involves extensive interaction with senior-level customers and requires the ability to develop long-term commercial relationships and drive business growth in international markets. Key Responsibilities
* Identify, develop, and manage new business opportunities in assigned international territories.
* Lead the full sales cycle, from initial market and customer engagement through negotiations, contract signing, delivery, and follow-on sales.
* Build and maintain strong relationships with senior clients and partners.
* Develop and execute territory-specific business development and sales strategies.
* Lead commercial negotiations and represent the company in meetings with customers and strategic partners.
* Coordinate cross-functional activities with Project Engineering, Operations, Finance, and other internal teams.
* Drive business development initiatives and ensure effective execution across organizational interfaces.
* Monitor market trends, customer requirements, competitive activity, and new business opportunities.
* Travel internationally on a regular basis, approximately 30% of the time.

Design high-performance analog and RF ICs optimized for precision, power, and area, driving prototype and product iterations from architecture to silicon validation.

Responsibilities
Design and simulate analog and RF integrated circuits, including critical blocks such as amplifiers, mixers, PLLs, ADCs, DACs, and bias/reference circuits, with a focus on signal integrity, linearity, and precision.

Optimize circuits for power, area, and performance trade-offs, ensuring designs meet system-level requirements across process, voltage, and temperature (PVT) variations.

Collaborate closely with optics, simulation and PCB teams to define architecture and block-level specifications for successive prototypes and product iterations, ensuring tight alignment with overall performance and integration goals.

Work with layout engineers to guide floor-planning and physical design, minimizing parasitic effects and preserving analog precision in layout-sensitive blocks.

Support post-silicon validation and bring-up, defining test plans, analyzing lab measurements, and correlating results with simulation to refine future design iterations.

Language: English at a proficient level. French is a plus.

As a Digital Backend Design Engineer, you will be responsible for the physical implementation of digital designs from RTL to GDSII, leveraging cutting-edge EDA tools and methodologies. You will collaborate closely with RTL design, DFT, and packaging teams to achieve optimal performance, power, and area (PPA), while meeting stringent timing and yield targets.

Responsibilities
Execute full-chip and block-level physical design tasks including floorplanning, placement, clock tree synthesis, routing, and physical verification.

Develop and optimize the digital backend flow.

Drive timing closure, power optimization, and physical verification (LVS/DRC/ERC).

Collaborate with front-end designers to address timing and logical/physical interface issues.

Support tapeout preparation and final signoff processes.

Play a critical role in ensuring the functional integrity, performance, and reliability of next-generation optical chips.

Responsibilities
Develop robust verification plans for complex digital and mixed-signal optical chip designs.

Collaborate closely with architects, designers, and customers to understand logic requirements, translate them into verification strategies, and deliver clear, actionable feedback throughout the development process.

Perform netlist-level simulations with SDF back-annotation for timing-accurate verification

Support FPGA/ASIC bring-up and post-silicon validation as needed

Develop, maintain, and optimize testbenches and verification components using advanced SystemVerilog features, such as constrained random testing, assertions, and transaction-level modeling, to create robust coverage-driven environments.

Design scalable, reusable UVM-based environments and components (e.g., agents, monitors, scoreboards) for block- and system-level verification. Employ UVM to achieve regression automation, functional coverage closure, and high bug-detection efficiency.

Develop and execute verification strategies for digital blocks implementing or interfacing with PCI Express (PCIe). Apply protocol-checking, compliance validation, error injection, and debug skills for PCIe endpoints and root complex devices. Use protocol analyzers and simulation environments to validate correct implementation across all protocol layers.

Participate in the verification of RISC-V CPU cores and subsystems. Create test plans targeting processor modules (ALU, decoder, register file, control logic), with reference model comparisons, signature checks, and coverage of edge-case scenarios. Leverage formal verification and compliance suites for thorough design validation.

Plan and perform end-to-end ASIC verification, from block-level testbenches to full-chip integration. Execute functional and regression tests, formal verification, and coverage analysis. Debug and resolve design issues, ensuring pre-silicon reliability before manufacturing. Engage in design reviews and system-level protocol validation with cross-functional teams.

Design and verify custom digital hardware components and architectures that enable high-performance, tightly integrated computation workloads and interface custom tensor unit for advanced AI/ML applications.

Responsibilities
Design, implement, and verify RTL blocks for memory, control, and compute subsystems within custom multiphysics computation unit.

Collaborate with system software and architecture teams to define block-level specifications and ensure alignment with performance and integration goals.

Develop and maintain functional verification infrastructure to validate design correctness across simulation and hardware testbenches.

Support synthesis, timing analysis, and backend integration, working closely with physical design and CAD engineers.

Contribute to architectural exploration and hardware-software co-design efforts to shape future iterations of compute platform.

As a Performance Software Engineer, you will be instrumental in building the core computation software that runs on custom AI accelerators. Your work will bridge the gap between host systems and proprietary hardware, encompassing everything from a custom on-board kernels to the sophisticated tooling required for real-time debugging. You will be a key player in chip bring-up and the long-term development of high-performance computation primitives and kernels, ensuring our architecture operates with maximum efficiency and deterministic performance.

Responsibilities
Develop and optimize low-level software primitives in C/C++, assembly, and architecture-specific intrinsics, primarily for RISC-V and ARM platforms.

Implement performance-critical kernels, runtime components, hardware abstraction layers, drivers, and firmware operating in bare-metal or highly constrained environments.

Work closely with hardware architects and RTL/design teams to define and validate hardware-software interfaces, memory maps, register interfaces, interrupts, synchronization mechanisms, and boot flows.

Analyze and optimize software for latency, throughput, memory footprint, instruction count, and efficient use of processor and accelerator features.

Bring up and debug software on simulation, emulation, FPGA, and silicon platforms, including low-level hardware/software integration issues.

Develop validation tests, benchmarks, and diagnostic tools for new processor, DSP, accelerator, and SoC functionality.

Contribute to architecture decisions around ISA extensions, compiler intrinsics, memory hierarchy, DMA, cache/coherency behavior, and software-visible hardware features.

As a Drivers & Virtualization Engineer, you will own the host-facing software boundary. Your mission is to ensure our hardware is accessible, secure, and performant across diverse environments-ranging from bare-metal deployments to complex virtualized and multi-device cloud infrastructures. You will focus on building robust kernel-level interfaces where correctness, isolation, and long-term operational safety are paramount.

Responsibilities
Develop and maintain high-performance Linux kernel drivers for proprietary accelerator.

Implement communication protocols and virtual device interfaces to bridge hardware and software.

Manage low-level hardware interactions including PCIe, DMA, MMIO, and interrupt handling.

Enable seamless virtualized access to accelerators using QEMU and KVM.

Design and implement robust device sharing, passthrough, and isolation mechanisms.

Ensure the security of accelerator operations through strict memory protection and resource isolation.

Debug complex failures that span the entire stack: from hardware and kernel to hypervisor and guest OS.

Support the scaling of our architecture from single-device setups to large-scale multi-device deployments.

Responsible for all marketing plans and executions for specific International countries and responsible with the sales director to the growth in the market

The main point contact for the market in all Marketing related topics

Work closely with the sales director responsible for that market and always know what is going on in the market, what are the objectives and what are their challenges

Build, update and execute Marketing plans according to the set objectives for the market

Ensuring all Sales Brand Managers & Education team are given proper and key information about marketing and kept in the loop on all matters

Present new launches and brand presentations to the distributors, their teams and internal teams

Monitor the success of launches, promotions and programs and be able to recommend actions based on this analysis

Ensure communications are consistent and on-brand for Professional Hair, Beauty Retail, and Travel Retail divisions

Edit Word and PDF files; mark/annotate changes for artwork rounds; promptly file completed projects. MUST be familiar with tracking and notation tools on Microsoft Word and Adobe Reader

Proofread and edit copy for primary and secondary packaging, i.e. description/romance, usage directions, ingredients, UPCs, and other compliance elements for global approval

Proofread materials according to INTL protocols, regulation and distributor information

Review translations based on source files. Occasionally route for stakeholder review and approval

ERP data support, maintain department data on ERP system

Manage supplier accounts (Israel and international), including invoice processing, payments, reconciliations, expense verification, and budget monitoring

Handle customer accounts (Israel and international), including issuing invoices and credit notes, tracking collections, and recording incoming payments

Process credit card transactions and record related expenses

Perform ongoing bank reconciliations

Maintain full-cycle bookkeeping and prepare balance sheets for audit purposes