לוח משרות דרושים מהנדסים בתל אביב יפו

We are now looking for a Senior Chip Design Integration Engineer to join our Switch Silicon team.As a Chip Design Engineer at our company's Networking business unit, you'll join a group of passionate engineers to design and implement the next generation state-of-the-art Switch Silicon chips. In this position, you'll make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!
What you'll be doing:
Work in a design/verification team which develops core units within the Switch silicon.
Micro-architecture of rtl/dynamic verification environments planning for units and modules.
Design RTL/dynamic verification environments of units/blocks according to Arch. specifications under challenging constraints with high orientation to power, area, and performance.
RTL synthesis, timing, supporting verification, and silicon post TO activities.
Work closely with multiple teams within organizations such as Architecture, u-arch, Full chip Micro-Architecture, BE, and FW.
Work in a FC team, responsible to integrate and verify the Switch at system level.

Our technology has no boundaries! we are building the worlds most groundbreaking and state of the art accelerated compute platforms for the world to use. Its because of our work that scientists, researchers and engineers can advance their ideas. We pioneered a supercharged form of computing loved by the fastest paced computer users in the world - scientists, designers, artists, and gamers.
We are seeking a highly motivated architect to join our team of experts and take part in shaping the future of high-performance and ML / AI computing. Our next-generation InfiniBand and NVLink systems will be at the heart of connecting and powering the world's most advanced compute clusters, from supercomputers used in AI research to high-performance clusters used at almost every industry today. As a system/software architect at our company, you will have the opportunity to work on some of the most innovative technology that is currently driving the world forward.
What youll be doing:
Define the next generations of our company's communication SW architecture.
Research of various solutions by defining and running POCs, evaluate SW and HW impact and conveying the solution architecture to the relevant teams. The solutions can span over various layers: from algorithms and high level software to firmware and HW.
Collaborate with multi-functional teams, including other architecture teams, VLSI logic design, system software, firmware, and research teams, to ensure the successful execution of the project.

We are now looking for a Senior Chip Design Engineer to join our Switch Silicon team. As a Chip Design Engineer at our company's Networking business unit, you'll join a group of passionate engineers to design and implement the next generation state-of-the-art Switch Silicon chips. In this position, you'll make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!
What You'll Be Doing:
Work in a design/verification team which develops core units within the Switch silicon.
Micro-architecture of rtl verification environments planning for units and modules.
Design RTL of units/blocks according to Arch. specifications under challenging constraints with high orientation to power, area, and performance.
RTL synthesis, timing, supporting verification, and silicon post TO activities.
Work closely with multiple teams within organizations such as Architecture, u-arch, Full chip Micro-Architecture, BE, and FW.

We are looking to hire a Chip Design Verification Manager to join our company's Chip Design group. The work environment is versatile, educational, dynamic and challenging as our employees are currently working on innovative, next-generation networking devices at the forefront of technology in terms of performance and power efficiency. Daily work involves all aspects of chip development: Design, Micro- Architecture, Firmware, and Verification. Work with the best and become one of the best!
What you will be doing:
Work in a combined design and verification team which develops core units within the Networking silicon.
Plan and Design Verification units/blocks according to Arch & Micro arch specifications under challenging constraints with high orientation to power, area, and performance.
Work closely with multiple teams within organizations such as Architecture, Micro- Architecture, FW and Post-Silicon validation.

'we are looking for an Asic Design Engineer to join the DFT design team and develop the next generation DFT technologies.
As a design engineer in the DFT design team at our company, you will participate in definition and implementation of our DFT technologies in various projects. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting Switches, Nic and SoC product lines. We are working closely with a wide range of aspects - chip design, backend, verification and production testing. We are working on the most advanced technologies and sophisticated products, our DFT solutions are unique, innovative, and we are continuously improving and evolving the solutions to meet the challenging goals.
What you'll be doing:
In this position, you will be responsible for defining, coding and integrating sophisticated DFT components into various projects and using state-of-the-art technologies.
As a member of our DFT design team, you will participate in defining various DFT features and improvements, write micro-architecture documents, code design blocks, integrate them into various projects, bring your design to silicon tape-out and silicon testing and production.
Strong collaboration with architects, other design teams, verification, back-end and production testing to accomplish your tasks.

we are looking for best-in-class Chip Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!
Come and take a significant part in designing and verifying our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a huge impact in a technology-focused company.
What you'll be doing:
Join the Tel Aviv group, working on designing the new generation of high-speed ports.
Design for chip blocks/entities according to specifications under challenging constraints and with high orientation to power, area, and performance
Daily work might involve any or all aspects of chip development: Verification, Design, and Micro-Architecture.
Work closely with Firmware and other groups around the globe.

we are looking for outstanding Chip Design Verification Engineers to join our Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!
Come and take a significant part in designing and verifying our ground-breaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a huge impact in a technology-focused company.
What you will be doing:
Join Tel Aviv group, working in a combined design and verification team which develops Phy Layer IP within the Networking silicon.
Build reference models, verify and simulate chip blocks/entities according to specifications and performance requirements.
Work closely with multiple teams within organizations such as Architecture, Micro- Architecture, FW and Post-Silicon validation.

We are seeking a Senior Deep Learning Researcher for an excellent opportunity! This role provides an outstanding opportunity to engage in groundbreaking innovation and contribute to advancing diffusion-based technologies. You will work with pioneering methodologies and tools, crafting solutions that push the boundaries of AI capabilities.
Joining our company means being part of a phenomenal team renowned for its inventions, such as our company Cosmos, Llama-Nemotron, Sana, and contributing to impactful work that influences various applications. We offer a collaborative environment that fosters professional growth. You will have the opportunity to collaborate with some of the brightest minds in the field, both within our company's global network and with leading companies worldwide, making this role perfect for those passionate about advancing AI technology and eager to make a significant impact on the future of the field.
What you'll be doing:
Invent and build ground-breaking techniques for efficient multi-modality model creation and publish the findings in leading journals and conferences.
Combine traditional diffusion technologies with the latest and greatest LLMs.
Contribute to our company's AI enterprise software to ensure robust and scalable solutions.
Collaborate with internal and external teams worldwide to drive research and development in multi-modal learning, using different professions and resources across the company.
Partner with leading scientific organizations and industry pioneers to remain at the forefront of technological advancements and integrate the latest innovations into practical applications.

our copmpany's Networking Clock design team is looking for experienced top notch ASIC design engineer to work on next generation of our company Networking chips. We're looking for profound and multi-disciplinary background in Clock design domains to lead Clocks Micro-Architecture activities. This role requires working with multiple teams as Architecture, IP, Physical design, Timing and Post-Si teams. Complexity of clocking scheme has grown substantially over recent chip generations with increased focus on performance, power and quality. Modern Clocking design needs to balance high frequency clocks with power, DFx, noise, circuit and physical design constraints.
What you will be doing:
Working on next generation of Networking Switch, NIC and SoC products.
Micro architect and design next generation clock topologies and modules.
ASIC Clock scheme definition.
Improve Power, Performance, and Area (PPA) of state-of-the-art company chips by evaluating trade-offs across DFx, Physical Implementation, Power Optimization and Ease of timing closure to innovate and implement new Clocking topologies in RTL.
Collaborate with Physical design and timing team to evaluate Clocking concerns and come up with solutions for supporting high speed Clocking.
Understand physical aspects of the chip and develop enhanced clock distribution techniques.
Get involved in end-to-end cycle of ASIC execution starting from micro-arch, design implementation, design fixes, sign-off checks and all the way to Silicon bringup.
Support Post-Si debug, characterization and productization activities.

we are seeking best-in-class ASIC Design Engineers to design and implement the worlds leading CPU's and SoC's. This position offers you the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. we are a learning machine that constantly evolves by adapting to new opportunities that are hard to pursue, that only we can take on, and that matter to the world. We have crafted a team of excellent people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.
we are building a new group in Israel, this group delivers security engines and risc-V processor IPs to all of our company's product lines working with all our company groups around the world. We are looking for inquisitive, motivated engineers with experience to continue to build this new group. As a senior member of our design team, you will be responsible for the design and implementation of high-performance, low-power security engines and risc-V processor modules. You will work closely with architects, design engineers, verification engineers, and physical design engineers to accomplish your tasks.
What you will be doing:
Participate in micro-architecture development and document specifications.
Implement in RTL and work with the verification team to ensure that the design is functional.
Apply logic design skills to optimize and meet performance and power goals.
Deliver a synthesis/timing clean design while working with the physical design team to ensure a routable and physically implementable design.

we are looking for a Senior Chip-Design Verification Engineer to join our Network Adapter Silicon group. As a Senior Verification Engineer at our company Networking Silicon team, you will join a group of passionate engineers to design and implement the next generation state-of-the-art Networking Silicon chips. In this position, you will make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!
What you'll be doing:
Work in a combined design and verification team which develops core units within the Networking silicon.
Build reference models, verify and simulate chip blocks/entities according to specifications and performance requirements.
Work closely with multiple teams within organizations such as Architecture, Micro- Architecture, FW and Post-Silicon validation.

Were looking for a Generative AI Developer to join our forward-thinking engineering team. This role is perfect for someone with a passion for cutting-edge AI, a strong software engineering background, and the creative spark to identify and implement novel use cases within our product.

What youll do:
Design, build, and deploy generative AI-powered features across our product.

Identify opportunities for AI integration by proactively exploring FinOps use cases and user needs

Prototype and validate new AI use cases quickly and iterate based on internal and external feedback

Collaborate cross-functionally with product, design, and backend teams to drive innovation from concept to production

Stay current with the fast-moving generative AI landscape and evaluate new models, APIs, and tools (e.g., OpenAI, Anthropic, Hugging Face, AWS Bedrock, open-source LLMs).

Live in the future and track new innovations and paradigms in this fast-evolving field, and identify opportunities to integrate them into the product

Implement safeguards, prompt engineering techniques, and usage monitoring to ensure high-quality AI outputs

Optimize model performance, inference time, and cost efficiency within AWS infrastructure

As a Senior DevOps Engineer , youll be at the forefront of shaping, operating, and scaling our production environments. Youll work closely with other engineering teams to ensure the reliability, scalability, and security of our platform, while continuously innovating and introducing modern, cutting-edge solutions.

Our workloads are fully Kubernetes-based, running on spot instances in a multi-cloud environment, with AWS as our primary cloud provider. Our architecture is stateless by design, leveraging cloud-native S3 for elastic storage and as a data lake. This enables advanced data pipelines with Airflow for data transformation and Clickhouse for high-speed queries.

This simple yet innovative architecture allows for rapid development iterations with minimal disruption to day-to-day operations, empowering constant optimization and high agility.

What Youll Do:
Proactively optimize and enhance delivery and live production environments

Partner with R&D teams by standardizing processes and providing self-serve tools for safe and fast execution

Establish and maintain efficient observability and visibility standards to support better decision-making across all teams

Enforce security and compliance best practices in day-to-day operations

Challenge and improve our technology stack by proactively introducing and developing new tools and approaches

our company's networking VLSI team is looking for a CAD engineering manager. The team is providing methodologies and vendor-based EDA flows for the physical design execution teams. Your team will be responsible for defining and developing methodologies and flows that enable high quality and super-efficient execution of over a hundred physical design engineers. You will be working closely with the physical design technology team, with design engineering professionals and project leads, and with peer software/CAD teams at our company, hence you will need to possess strong interpersonal skills, be a quick learner, and manage multiple missions in a results-oriented manner. You, along with the team, will lead processes from requirements understanding, through software definition and implementation of tools/flows, ending with release, integration and support.
What you'll be doing:
Lead a growing team of ~5 professional CAD engineers.
Own the definition, development, and maintenance of software solutions for physical design engineering.
Collaborate and closely interact with design technology experts and execution engineers, along with software/CAD peers.
Influence and make right choices to produce high quality and tangible impact.
Be agile and make continuous and incremental progress by decomposing the problem in to smaller and achievable goals
Define and build strategic vision for the networking VLSI technology and EDA team.

Today, were tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing whats never been done before takes vision, innovation, and the worlds best talent. As a worker, youll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world.
The complexity of the chip has greatly increased over the years. We are now packing tens of billions of transistors in a chip to meet the growing computing demand in a footprint that is responsible to our environment. The our company's System-On-Chip (SOC) group is looking for a top physical design engineer with a curiosity about SOC design optimization, physical integration, chip build and assembly and verification. You should have real passion for methodologies and clock distribution solutions that enable SOC creation in the most optimized way. In this position, you will get the opportunity to build complex networking chips and directly contact unit-level owners, Physical Design, CAD, Package Design, Software, DFT and other teams.
What you'll be doing:
Designing and implementing SOC level clock requirements
Daily work involves aspects of chip level design, including partitioning, CDC, trial synthesis, design quality checks
Be exposed and work on a variety of functional and structural challenges. Including functional debug, physical design readiness, resolve design quality issues.