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Required DFT Engineer
Job Description
Meet the Team
We are a leading Design for Test (DFT) group, delivering End-to-End solutions for our flagship products, including CiscoSilicon One!. Our chips are strategically placed in critical AI infrastructure, powering next-generation network devices and supporting advanced AI workloads. We push the boundaries of technology, developing innovative DFT solutions that drive industry-leading programmability, scalability, and performance.
Our team operates in a hybrid model, with three days a week in the office in Azrieli Tower Tel Aviv or Caesarea, fostering collaboration and technical excellence in a startup-like atmosphere within a stable, global corporation!.
Your Impact
Expand Your Scope- we provide engineers from different backgrounds the environment to master, standardize and evolve across different features.
Lead hands-on execution from pre-silicon design to silicon bring-up and production.
Collaborate with architects and verification teams to define the DFT roadmap for our next-gen Silicon One chips.

Were looking for a highly effective and experienced Backend Python Engineer with deep Python expertise to design and deliver scalable, resilient systems as part of a highly successful and collaborative engineering team.


In this role, you will work on highly innovative, next-generation security technologies within our Human Risk Management (HRM) product group. Human Risk Management is a comprehensive approach to cybersecurity that focuses on understanding, measuring, and mitigating risks associated with human behaviour across an organization.


You will contribute in technical design and code quality, and will be responsible for designing and building a new, large-scale analytics database from the ground up, forming a core foundation of our risk scoring and HRM capabilities. This is a hands-on role with meaningful ownership across the full software development lifecycle.


Your day-to-day:

Lead the design and development of core backend components of a large-scale SaaS platform using Python.

Design, build, and maintain RESTful APIs and highly available management services.

Design and implement scalable distributed systems and intelligent network data-path processing.

Design, build, and evolve a new large-scale analytics database from the ground up, responsible for ingesting high-volume security signals and calculating human risk scores at scale.

Champion engineering best practices, system reliability, and maintainable code.

Contribute to in-depth code reviews, architectural guidance, and mentoring of other engineers.

We are looking for an experienced Design Verification engineer to join our DFT team and help establish and grow DFT DV activity in the SiliconOne DFT team. This role is relevant for engineers with experience in DV roles, either in DFT DV or in other verification domains, who are interested in becoming familiar with DFT design, verification methodologies, and the challenges of validating testability features in advanced silicon.
Your Impact
Establish and drive DFT verification activities within the SiliconOne DFT team.
Develop verification plans, environments, checkers, assertions, and coverage models for DFT features.
Verify DFT architecture and implementation in close collaboration with DFT, design, architecture, and verification teams.
Work on verification of scan, MBIST, IJTAG/JTAG, test access mechanisms, DFT controllers, and related SoC-level test features.
Debug complex pre-silicon issues across RTL, verification environments, and DFT logic.
Contribute to scalable methodologies, reusable verification components, and best practices for DFT DV.
Help bridge between general DV methodologies and DFT-specific design and verification needs.

Required DFT Engineer
Job Description
Meet the Team
We are a leading Design for Test (DFT) group, delivering End-to-End solutions for our flagship products, including Silicon One!. Our chips are strategically placed in critical AI infrastructure, powering next-generation network devices and supporting advanced AI workloads. We push the boundaries of technology, developing innovative DFT solutions that drive industry-leading programmability, scalability, and performance.
Our team operates in a hybrid model, with three days a week in the office in Azrieli Tower Tel Aviv or Caesarea, fostering collaboration and technical excellence in a startup-like atmosphere within a stable, global corporation!.
Your Impact:
Expand Your Scope- we provide engineers from different backgrounds the environment to master, standardize and evolve across different features.
Lead hands-on execution from pre-silicon design to silicon bring-up and production.
Collaborate with architects and verification teams to define the DFT roadmap for our next-gen Silicon One chips.

We are seeking an experienced and highly motivated C++ Software Engineer to join the Compiler team of our Network Technology R&D organization, contributing directly to the evolution of next-generation networking products.
Meet the Team
Our team builds firmware, SDKs, simulators, and compilers for the architecture - the industrys first routing and switching silicon architecture unifying networking across all layers. You will work on pioneering technology that powers the future of the Internet.
You will be part of a global team working on the newest generation, which will be integrated across the entire portfolio of our devices.
You will collaborate with worldwide distributed R&D centers, gaining exposure to some of the most talented engineers in the networking industry. We look for people who love technology and engineering-people who thrive on innovation, continuous learning, and challenging whats possible.
Your Impact
Design, implement, and test a state-of-the-art optimizing compiler for us
Evaluate and optimize code performance, including debugging, code generation improvements, and pipeline analysis
Develop, optimize, and enhance the compiler backend to fully leverage cutting-edge hardware capabilities
Solve complex resource management challenges across hardware pipelines
Design and implement new P4 language features that empower network application developers
Build and maintain the compiler toolchain for custom networking applications
Contribute to libraries, analysis tools, and supporting infrastructure
Collaborate with cross-functional hardware and software teams
Work closely with ASIC engineers on next-generation IC design, influencing hardware through compiler insights prior to tape-out.

We are looking for a top-notch Sr software automation engineer to drive our test efforts and automation infrastructure. You will be in charge of, first and foremost, product quality, design and plan required quality assurance tests, you will develop automation tests and needed infrastructure together with deployment to all known cloud providers using python, and working closely with a development team to address issues that were discovered. Additionally, you will be involved in developing test infrastructure for Unit-Tests, Integration-Tests and more, while providing the infrastructure as a service to the dev teams. The job is deeply hands-on and requires a deep understanding of the product, and the environments it runs.
Your Impact
Work closely with our engineering teams to understand business requirements
Own and develop test infrastructure used by dev teams, while providing them with guidance and assistance for using it
Design, plan and implement automatic tests for our critical business paths
Own and adjust our UI testing framework to support dev teams which are using it to develop end-to-end tests
Own and improve peripheral tools for our quality efforts, such as reporting, investigation etc.
Identifying, reporting, documenting and tracking defect/bug issues
Investigate, analyze and find the root causes for failed systems and software
Ability to effectively communicate with all levels of the organization
Excellent verbal and written communication skills.

We are seeking a Physical Design Manager.
Meet the Team:
Physical Design team within Silicon One is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.
We demonstrate the latest silicon technologies and processes to build the largest-scale and most complex devices, pushing the boundaries of feasibility.
Your Impact:
You'll be part of the Silicon One team, which is at the heart of our software and ASIC design efforts.
As the Physical Design Manager, you will provide strategic and technical leadership to a team of engineers, guiding them through the entire chip design lifecycle. You will be responsible for the group's output, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.

As a Pre-Sales Engineer for SOC Transformation you will be the expert for our Cortex portfolio, a Next-Gen AI-powered security operations platform. You will play a key role in defining technical solutions that secure a customers key business imperatives.
You evangelize our industry leading solutions in Security Intelligence and Automation, XDR, Attack Surface Management, XSOAR, and Incident Response that establish Palo Alto Networks as a customers cybersecurity partner of choice. Additionally, lead CloudSec Transformation with expertise in Posture Management, Cloud Detection & Response, AppSec, and other key areas, ultimately establishing Palo Alto Networks as the cybersecurity partner of choice.
Your Impact
Collaborate with account teams to recommend and develop customer solutions within your assigned specialization area
Present to customers as our expert at all levels in the customer hierarchy, from practitioner to senior leadership
Lead and support customer demonstrations that showcase our unique value proposition
Scope and Lead Proof of Value (PoV) projects for prospective customers based on best practices to ensure technical win in your assigned opportunities
Drive high technical validation and PoV win rates within your assigned specialization area
Architect solutions that will help our customers strengthen and simplify their security posture
Accelerate technical validation of proposed solutions within your specialization
Document High-Level Design and Key Use Cases to ensure proper implementation and value realization of Palo Alto Networks Solutions
Help our customers build and develop further their services around Cortex solutions
Lead conversations about industry trends and emerging changes to the security landscape
Discuss, with credibility, competitive offers in the marketplace and position ours as the best alternative
Assist account solutions consultants to respond effectively to RFIs/RFPs while serving as the main technical point of contact for Cortex
Position Palo Alto Networks or Partner-delivered services as appropriate to ensure proper implementation and value realization of Palo Alto Networks solutions.

Required ASIC Leader
Meet the Team
Join the Silicon One Front-End Design team, at the core of our silicon development. Our engineers cover the full spectrum of chip design: definition, architecture, micro-architecture, RTL design, verification, signoff, and validation.
We leverage cutting-edge silicon technologies and methodologies to develop the largest-scale and most advanced devices, pushing the boundaries of whats possible.
We are transforming the industry with a unified, programmable architecture powering our future routing portfolio and shaping the Internet for decades to come.
Your Impact
Review micro-architecture specifications
Supervise verification team members and provide professional guidance
Implement Verification environment UVM based
Collaborate with Design engineers to resolve bugs and achieve coverage closure
Work with the firmware/Lab teams to verify chip flows
Perform debug, root-cause analysis, and post-silicon validation in the lab.

We are looking for a highly motivated and customer-focused professional. As part of the Tier 3 Cortex XDR support team, you will serve our customer base by providing technical support, by answering incoming support inquiries and managing escalations, phone calls, and emails in an effective, efficient, and friendly manner within defined service level agreements.
Our methodology is first class support. Weve been recognized for it as an industry leader and were dedicated to continuing this standard. In this role, you will work with our technical account managers to personalize our customers experience. You will learn your clients business objectives in and out within their technical environment and focus on mitigating risks and resolving any technical issues in their networks. Youre close to the deployment of cybersecurity solutions - and we need you to recognize risks before they arise. You get a thrill from seeking out complex issues and finding their resolutions - and you dont wait for those issues to escalate from our clients. Instead, you find them. Youll be working hand in hand with our developers to reproduce the issues you find and develop permanent solutions to prevent them in the future.
Key Responsibilities
Respond to customer-reported issues in adherence to established Service Level Agreements
Triage customer reported issues and respond to them via ticketing system, phone, or remote sessions
Perform advanced troubleshooting at the application level and OS level, using your knowledge and relevant expertise
Identify the area of fault (code, environment, or configuration) and work with the appropriate team(s), characterizing and implementing the fix
Provide timely feedback on the development process on customer-reported product problems
Document actions to effectively communicate information internally and to customers
Facilitate root cause investigations and manage the implementation of corrective and preventative measures.

We are seeking PHY Algorithm Technical Leader, Silicon One Israel
Meet the Team:
You will join the SerDes System Algorithm team within Silicon One High Speed in Israel, part of our silicon development organization. The team works across modem technology, system modeling, and signal processing for high-speed SerDes devices.
We are at the center of our ASIC group, building next-generation network devices for AI networks, the 5G era, and the future of routing. Our design center brings silicon hardware and software disciplines together in one site, combining a small-team startup atmosphere with the scale and stability.
Your Impact:
As a PHY Algorithm Technical Leader, you will provide technical leadership for the development, modeling, configuration, and optimization of algorithms for advanced SerDes modem systems. You will work with the latest silicon technologies and processes to help build large-scale, complex devices at the edge of feasibility.
Your work will contribute to Silicon One, a unified and programmable silicon architecture designed for service provider and web-scale markets. The role requires technical depth in digital signal processing, modem behavior, and using MATLAB for algorithm development, with the ability to guide algorithm work from initial concept through advanced SerDes system implementation.
Provide technical leadership for research, design, and development of PHY and modem algorithms for high-speed SerDes devices.
Define and use system models to analyze modem behavior, signal-processing performance, architecture constraints, and algorithm tradeoffs.
Guide modem configuration, tuning, and optimization to improve performance, robustness, and implementation feasibility.
Use MATLAB for algorithm development, simulation, testing, and data analysis.
Guide technical decisions, review algorithm tradeoffs, and mentor engineers on complex PHY and modem development tasks.
Lead cross-functional technical collaboration with system, silicon hardware, and software teams to move algorithms from modeling into practical implementation.
Support lab-based validation and debug activities when required.

Required Logic Design Engineer
Job Description
Meet the Team
Join the Silicon One Front-End Design team, at the core of our silicon development. Our engineers cover the full spectrum of chip design: definition, architecture, micro-architecture, RTL design, verification, signoff, and validation.
We leverage cutting-edge silicon technologies and methodologies to develop the largest-scale and most advanced devices, pushing the boundaries of whats possible.
We are transforming the industry with a unified, programmable architecture powering our future routing portfolio and shaping the Internet for decades to come.
Your Impact:
Write and review micro-architecture specifications
Implement RTL (Verilog/SystemVerilog) to meet timing, performance, and power requirements
Contribute to full chip integration, timing methodology, and analysis
Collaborate with verification engineers to resolve bugs and achieve coverage closure
Work with the physical design team to close timing and PnR issues
Support design methodology evolution and best practices
Perform debug, root-cause analysis, and post-silicon validation in the lab.

Required PHY Firmware Technical Leader
Meet the Team:
Join the Silicon One PHY System team, part of our core silicon development group.
Our team is responsible for PHY and system-level aspects of some of the most advanced networking devices in the industry, including PHY firmware, calibrations, system definitions, operations, and post-silicon validation.
We work with the latest silicon technologies and processes to build large-scale, highly complex devices at the edge of feasibility. Youll be part of a unique design center that hosts all silicon HW and SW disciplines under one roof, operating in a startup-like environment within a stable, world-leading company.
We are transforming the industry with a unified, programmable silicon architecture that powers our future routing portfolio and helps shape the Internet for decades to come.
Your Impact:
Develop PHY firmware and system-level features for advanced networking ASICs
Participate in post-silicon validation, including lab bring-up, debugging, and performance analysis
Collaborate closely with PHY, system, firmware, and silicon design teams
Contribute to defining system operation modes and end-to-end device behavior
Help drive the development of next-generation, high-scale networking solutions using cutting-edge silicon technologies
Who Youll Work With:
The Silicon One group, the center of our ASIC design efforts
Cross-functional teams including silicon design, firmware, and system
Global teams working together to deliver game-changing networking devices.

We are seeking a CAD Engineer to join the Silicon One Physical Design team.
Meet the Team:
You'll be part of the Silicon One team, which is at the heart of our software and ASIC design efforts.
As part of our team, youll contribute to the development of our next-generation network devices. Our team operates in a startup-like environment within a stable and leading corporation.
Our design center is uniquely equipped, hosting all silicon hardware and software development fields under one roof.
We are revolutionizing the industry by building a new internet for the 5G era, providing a unified, programmable silicon architecture that serves as the foundation for all of our future routing products. Our devices are designed to be universally adaptable across service providers and web-scale markets, catering to both fixed and modular platforms. They deliver high speed without compromising on programmability, buffering, power efficiency, scale, or feature flexibility.
We are a ground-breaking, groundbreaking technology that will serve our customers and end users for decades to come. The Internet now has a new, faster, better, and safer engine!
Your Impact:
You'll be joining our Physical Design team within Silicon One, which is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.
Our Backend Engineers handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.
You will be leveraging your backend and physical design experience to drive the development, optimization, and innovation of CAD methodologies and tools, ensuring the highest quality and efficiency in our chip design flows from RTL to GDS.

We are seeking a CAD Engineer to join the Silicon One Physical Design team.
Meet the Team:
You'll be part of the Silicon One team, which is at the heart of our software and ASIC design efforts.
As part of our team, youll contribute to the development of our next-generation network devices. Our team operates in a startup-like environment within a stable and leading corporation.
Our design center is uniquely equipped, hosting all silicon hardware and software development fields under one roof.
We are revolutionizing the industry by building a new internet for the 5G era, providing a unified, programmable silicon architecture that serves as the foundation for all of our future routing products. Our devices are designed to be universally adaptable across service providers and web-scale markets, catering to both fixed and modular platforms. They deliver high speed without compromising on programmability, buffering, power efficiency, scale, or feature flexibility.
We are a ground-breaking, groundbreaking technology that will serve our customers and end users for decades to come. The Internet now has a new, faster, better, and safer engine!
Your Impact:
You'll be joining our Physical Design team within Silicon One, which is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.
Our Backend Engineers handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.
You will be the tech lead for CAD within the team, leveraging your extensive backend and physical design experience to drive the development, optimization, and innovation of CAD methodologies and tools, ensuring the highest quality and efficiency in our chip design flows from RTL to GDS.
We demonstrate the latest silicon technologies and processes to build the largest-scale and most complex devices, pushing the boundaries of feasibility.