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We are looking for a brilliant system engineer to join Wiliot and help to scale the world of IoT.
As a system engineer, you will work on various innovative fields from RF automation, algorithms., channel usage optimizations, energy consumption optimization and dynamic network development.

we are looking for a Senior Machine Learning Engineer to work on LLM-based systems with a strong emphasis on integration, end-to-end workflows, and production readiness. This role combines performance optimization (prefill/decode, throughput, latency) with hands-on work integrating components across the AI platform.
A significant part of the role involves building end-to-end integration flows and tests, particularly around token generation pipelines and system orchestration, as well as contributing to intelligent system behavior such as hardware selection and execution strategies. The role also includes developing system-level logic in Python for multi-tenant management, caching strategies, and service lifecycle management across the platform.
***This is not a Data Science position***
Responsibilities:
Build and maintain end-to-end integration flows across the AI inference pipeline (serving, orchestration, APIs, and infrastructure)
Design, implement, and optimize LLM inference workflows, including prefill and decode stages
Improve system performance with focus on throughput, latency, and interactivity
Write production-grade components in Python and integrate them into the broader system
Contribute to system-level logic such as smart hardware selection and execution strategies
Integrate models (open source and custom), services, and APIs into cohesive, reliable end-to-end application pipelines

we are seeking a Lead System Architect to join our system architecture team and help define the next generation of our AI-SuperNIC scale-out chip.
AI scale-out communication is a critical element in modern data centers, and emerging standards such as Ultra Ethernet aim to address this challenge. This role focuses on defining a high-performance Smart NIC architecture optimized for GPU-centric AI workloads, with emphasis on low-latency, high-bandwidth data movement.
You will work across hardware and software domains, collaborating closely with AI, platform, driver, and VLSI teams to design a competitive scale-out networking solution.
Responsibilities:
Define product requirements and architecture for next-generation ultra low-latency AI-SuperNIC
Design end-to-end data paths across NIC, host, and GPU memory, with focus on GPU connectivity (PCIe, NVLink, CXL)
Lead adoption of emerging standards such as UEC and UALink, while maintaining compatibility with existing ecosystems
Establish architecture guidelines and partitioning across hardware, firmware, and software
Drive performance modeling, analysis, and system-level optimization for AI workloads
Optimize scale-out communication patterns (e.g., collectives) for GenAI training and inference
Collaborate with software teams on drivers, runtimes, and integration with AI frameworks
Work with R&D, CTO, and peer architects on system definition and trade-offs
Engage with customers and partners to shape system requirements and use cases

As a Project Management Student with us, youll find motivation and inspiration in a culture that emphasizes passion for patients as you discover your own strengths.

How you will make an impact:
Track and manage project tasks, action items, and deliverables.
Prepare weekly and monthly project status updates (dashboards, presentations, progress reports, budget tracking support).
Coordinate meetings, including agenda preparation and meeting minutes.
Monitor dependencies and execution progress across multiple stakeholders (Business Units, IT, external vendors - as applicable).
Maintain and update project data in Jira as the designated task management tool.
Support the setup and maintenance of basic project management infrastructure.
Provide ongoing execution and operational support to the project team.
Supports day‑to‑day execution in collaboration with the Project Lead.
Interfaces with cross‑functional internal teams and external partners as needed.

Job Summary:

Identifying and attracting talents for vacancies in Israel. Advise management, develop and facilitate programs to enable us to meet talent acquisition needs.


How you'll make an impact:

Managing the recruitment cycle for assigned vacancies in Israel.

Partner with hiring managers to set recruitment process planning and expectations (key requirements and competencies, sourcing strategy, recruitment strategy etc.).

Open and post vacancies in the internal Applicant Tracking System (Workday) and other job boards.

Develop multiple talent sourcing options for both active and passive candidates, utilize advanced sourcing techniques to identify candidates (e.g., cold calling, job boards, advertising, database and internet searches, and networking and referrals).

Manage relationship with recruitment agencies to make sure our needs have been clearly identified and met.

Performs candidate screening (review resumes, phone calls, competency based interviews), identifying position matching, availability, interest level, salary range, relocation needs etc.

Coordinate candidates interview calendar and travel arrangements with hiring manager and other stakeholders involved in the recruitment project.

Identify and execute the most appropriate assessment tests for any defined position.

Collaborate with Country HR, HRBPs and hiring managers to conduct moderately complex offer negotiations and finalize the hiring process.

Lead portions of strategic talent acquisition projects, processes and programs to fulfill business needs and organizational priorities.

Manage vendor services to ensure services are in keeping with expected service levels, assuring that contracted work is fulfilled, and identifying issues for escalation.

Develop content on recruitment/talent acquisition processes and provide training to stakeholders.

Other incidental duties.

we are looking for a senior VLSI Design Engineer highly experienced in developing designs for complex SoC devices, from arch/uarch definition to coding and verification. In this position you will have end-to-end responsibility for all design flow. In this position you will be responsible for full cluster/block uarch, design, initial synth, lint, integrating and supporting PD, DFT and verification.
If you are curious, innovative, have strong technical skills with a hands-on approach, and understand the full design, system view and SW integration requirements, this position is for you!

We are looking for a Senior Verification Engineer to be a significant part in developing a complex and innovative SoC chip in a start-up company.
Taking full ownership of entire domain, defining the verification strategy, writing, and executing verification plan in system Verilog UVM.