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seeking a Lead Networking Architect to help define and shape the next generation of our AI-SuperNIC scale-out chip.

Scale-out communication is a critical element in building competitive systems for modern data centers. Were looking for an expert with deep networking experience to collaborate closely with our AI/ML, platform and driver software, and VLSI teams in designing an optimized scale-out networking architecture.

If youre passionate about low-latency communication and have a strong background in RoCEv2, HPC communication, and NVMe-oF, this is a unique opportunity to take on a challenging and influential role.

This is a senior, high-impact position at the forefront of technology innovation-driving the development of cutting-edge networking and AI acceleration solutions.

Responsibilities

Work closely with CTO and peer architects to define the product requirements and features of next generation ultra low-latency AI-SuperNIC scale-out chip
Lead adoption of new industry standards such as UEC, UALink while maintaining a competitive solution for RoCEv2
Establish architecture guidelines, requirements, and the division of labor between software, firmware and hardware.
Lead performance estimations, modeling, measurements, and optimizations, as well as system-level integration efforts.
Engage directly with end customers and partners to shape use cases and system solutions.

We are looking for a hands-on, experienced Physical Design Engineer to join us and help define and implement next-generation AI SoC in an advanced technology node

You will play a key role in building and leading our physical design team, developing flows and methodologies, and driving the full RTL-to-GDSII implementation and signoff for one of the most advanced SoCs in the industry.

What Youll Do

Take part in shaping methodology and best practices in advanced technologies

Drive end-to-end implementation: synthesis, P&R, timing closure, and signoff

Collaborate closely with architecture and design teams on timing, floorplaning, partitioning, and power specification

Define and optimize static timing constraints, area, and power goals at block and top levels

Take part in flow development and automation to improve efficiency and quality of results

seeking a Director of Product Management with experience supporting the development of a large-scale SoCs or NICs (inbound & outbound. As a product leader, you will lead product definition and vision and launch products from start to finish. You will drive interactions with engineering teams, lead customer discussions, develop go-to-market strategies, identify new markets, and work with senior leaders on the vision and customer impact.

If youre passionate about shaping the future of AI chips and thrive in a collaborative, hands-on environment, this position is for you!

Responsibilities

Execute product development and delivery by working with cross-functional teams (R&D, sales, operations, and corporate development) to ensure successful product launch and business growth
Build close relationships with lead customers and manage product engagement and support
Assist with the Go-to-market strategy and launch plan with a clear market assessment, competitive analysis, and positioning of products
Develop compelling sales material that clearly promotes product value and differentiation, and work closely with sales and customers to secure new business opportunities and close design wins.
Maximize Business Impact through continuous market assessment. Refine product, when needed, based on new learnings and as an advocate for the customer

We are looking for a talented Senior Networking Engineer to be a significant part of developing and designing software for complex SoC developed. Take part in architecture and defining HW-SW interfaces. Design and implement networking stacks on embedded cores as part of a high throughput complex multi-threaded environment.

Our group is responsible for the development of next generation SoC for AI Networking Compute . The development starts from product definition through architecture, design, verification and up to implementation.

The complex SoC is a high-performance device running AI scale-out for inference workloads computer for vision and audio processing, with technologies from multi-disciplines.

We are looking for a Senior Verification Engineer to be a significant part in developing a complex and innovative SoC chip in a start-up company.

Taking full ownership of entire domain, defining the verification strategy, writing, and executing verification plan in system Verilog UVM.

Overview:

We are looking for a hands-on senior engineer to own the end-to-end productionization of Real-Time video systems and AI pipelines.

This role is not research and not model invention.

You will take existing computer vision models and algorithmics and integrate them into production, turning them into high-performance, scalable, production-grade systems running across hundreds of concurrent video streams on GPU and edge hardware.

You will work at the intersection of:

Python microservices backend development
video streaming using GStreamer and NVIDIA DeepStream
Distributed and multithreaded development
Real-Time inference
AI pipeline/processing optimization
Deploy and accelerate CV and AI models using CUDA, TensorRT, PyTorch, OpenCV

This is a deeply engineering-focused role with real ownership.