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The CPU Architect will take charge in defining a processor core that meets the requirement of high performance, high bandwidth, and scalable processing architecture. This architect will utilize his processor experience to deliver a world-class processor ASIC with many advanced features for Huawei products.

Our goal is to design cutting-edge CPUs for smartphones, servers, and desktops, and we need the very best talent to help us achieve it!
The CPU Architect will take charge of defining a processor on chip inter-connect and coherent fabric that meets the requirement of high performance, high bandwidth, and scalable processing architecture. This architect will utilize his processor experience to deliver a world-class processor ASIC with many advanced features for Huawei products.

as a quality and reliability (q&r) engineer, you will lead the qualification and long-term reliability of advanced system -on-chip ( SOC ) and RF semiconductor products for automotive applications. youll work across digital and RF domains to ensure robust performance and compliance with industry standards.
what will your job look like:
define and manage quality and reliability specifications, simulations, and qualification plans for SOC and RF die and package.
plan and execute automotive-grade qualifications per standards such as aec-q100, jedec jesd22, and iatf 16949.
design and implement die-level and package-level stress tests.
select and prepare electrical, environmental, and mechanical TEST platforms for reliability testing.
define requirements for pre-si q&r (e.g. esd, lu, em, ir drop), design-for- TEST (dft), electrical characterization, and post-si q&r testing of digital, mixed-signal and RF socs.
collaborate extensively with internal design teams, external subcontractors, and outsourcing partners (osats).
lead failure analysis, reliability modeling, and corrective action processes (e.g., 8d, fmea, fmeda).
document and certify automotive standards compliance, including ppap/apqp deliverables.

Our SOC verification group owns the important and challenging job of verifying mobileye's chip. it is involved from product specification to final SOC delivery, and involves all the system components. the group is made up of few of the best Verification engineers, so besides contributing to making our roads safer, youll get the chance to work at one of the most professional verification teams.
what will your job look like:
you'll be responsible for pre-silicon system -level verification of the most cutting-edge ai accelerators and technologies in the automotive field.
define the testplan, develop and run tests on simulation/emulation environments, develop TEST environment and verification collaterals.
you'll have a broad effect on our unique product from the very beginning of the process.

which department will you join?
our hw team - a group designing the eyeq chips for adas and autonomous cars. the group is responsible for all disciplines of development, including but not limited to logic design, design verification, microarchitecture, analog and circuit design and layout, physical and structural design ( backend ), product and TEST engineering.
each physical design engineer has an end to end responsibility from definition, execution & full signoffs, working closely with design & architecture teams for constraints development, design review & rtl modifications to achieve converges were looking for a physical design engineer to join the growing physical design team, responsible for state of the art SOC design from definition to tape-out. what will your job look like:
hands-on physical design block owner from rtl to gds.
floorplan exploration with guidance and collaboration with Front-End and architecture teams.
sta: work with fe and floor planner to manage block and top level constraints and 1st level of timing analysis.
synthesis exploration and final synthesis netlist: scan insertion @ synthesis, clean checks from lint, upf & spyglass.
place & route: from synthesis netlist to final layout and signoff verification with target to achieve best power performance and area.

which department will you join?
epg is a fast-paced, dynamic, and startup-like group responsible for researching, incubating and developing next-generation technologies and ideas, with a strong orientation towards computer vision, Machine Learning, data, and ai.
the group hosts a diverse team of scientists, engineers and developers to research, realize, and bring to market innovative new products, leveraging cutting-edge technologies, skills and capabilities.
were looking for a backend expert to join the growing physical design team, responsible for state of the art SOC design from definition to tape-out.
what will your job look like:
hands-on physical design block owner from rtl to gds.
floorplan exploration with guidance and collaboration with Front-End and architecture teams.
sta: work with fe and floor planner to manage block and top level constraints and 1st level of timing analysis.
synthesis exploration and final synthesis netlist: scan insertion @ synthesis, clean checks from lint, upf & spyglass.
place & route: from synthesis netlist to final layout and signoff verification with target to achieve best power performance and area.

about the job
be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
the ai and infrastructure team is redefining whats possible. we empower our company customers with breakthrough capabilities and insights by delivering ai and infrastructure at unparalleled scale, efficiency, reliability and velocity. our customers, our company cloud customers, and billions of our company users worldwide. we're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge ai models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. from software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our tpus, vertex ai for our company cloud, our company global networking, data center operations, systems research, and much more.
responsibilities
collaborate with architecture, design, and verification teams to develop new product bring-up, validation, characterization, and qualification strategies, manufacturing TEST solutions for new high performance computing (hpc) products in advanced process technologies.
verify TEST solutions on pre-silicon models (simulation or emulation) and develop ate TEST modules, dc tests, binning, production flows, and characterization flows.
develop and validate TEST programs on ate platforms for new product integration (npi) in preparation for high volume manufacturing (hvm), working with ate vendors.
support product sustainability, including volume data analysis of screening and characterization data, TEST time and yield improvements, TEST escapees and return merchandise authorizations (rmas) assessments, failure localization, containment measure implementation, and partnership with design manufacturing, quality, and reliability teams to root cause and implement corrective actions.
develop tools, flows, and methodologies to continuously improve and automate the testing.

you will collaborate closely with design and Verification engineers in active projects, creating architecture definitions with rtl coding, and running block level simulations.as a design & power methodology team manager within the server chip design team, you will be responsible of managing and leading design and power methodologies from ip to SOC, pre and post silicon. you will be responsible for mentoring and developing team members and tech leads while driving improvements in leadership, technical execution, and design flows.you will work closely with cad vendors and internal teams to develop lead design and power methodology and execution.the ai and infrastructure team is redefining whats possible. we empower google customers with breakthrough capabilities and insights by delivering ai and infrastructure at unparalleled scale, efficiency, reliability and velocity. our customers include googlers, google cloud customers, and billions of google users worldwide. we're the driving force behind google's groundbreaking innovations, empowering the development of our cutting-edge ai models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. from software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our tpus, vertex ai for google cloud, google global networking, data center operations, systems research, and much more.
responsibilities
manage a team of tech leads and designers. develop and mentor team members, and communicate and co-work with multi-disciplined and multi-site teams.
lead flow and methodology development and assimilation across multiple groups. work closely with cad tool providers as well as internal cad teams.
plan, execute, track progress, assure quality, and report status.
work closely with internal customers and support multiple activities and deliverables.
drive design methodologies such as design construction, cdc, rdc, sdc. drive power at: ip and SOC rtl/gate level optimization, estimation, correlation.

about the job
be part of a team that pushes boundaries, developing custom silicon solutions that power the future of google's direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
google system infrastructure builds the cloud for google services and for google cloud customers, by solving business TEST of performance and cost, utilizing hardware, software, and system solutions.the ai and infrastructure team is redefining whats possible. we empower google customers with breakthrough capabilities and insights by delivering ai and infrastructure at unparalleled scale, efficiency, reliability and velocity. our customers include googlers, google cloud customers, and billions of google users worldwide. we're the driving team behind google's groundbreaking innovations, empowering the development of our cutting-edge ai models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. from software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our tpus, vertex ai for google cloud, google global networking, data center operations, systems research, and much more.
responsibilities
plan the verification strategy, identify the platform to validate reasoning components.
define the TEST plan and strategy with stakeholders, including sign-off and exit criteria.
plan and execute the verification of internet protocols (ips) using dynamic verification and formal verification.

about the job
be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
in this role, you will be part of a team developing application-specific integrated circuits (asics) used to accelerate networking in data centers. you will have multiple responsibilities in areas such as project definition, design, and implementation. you will participate in the design, architecture, documentation, and implementation of the next generation of data center accelerators.you will also be responsible for performance analysis for a networking stack using your knowledge.the ml, systems, & cloud ai (msca) organization at our company designs, implements, and manages the hardware, software, Machine Learning, and systems infrastructure for all our company services (search, youtube, etc.) and our company cloud. our end users, cloud customers and the billions of people who use our company services around the world. we prioritize security, efficiency, and reliability across everything we do - from developing our latest tpus to running a global network, while driving towards shaping the future of hyperscale computing. our global impact spans software and hardware, including our company clouds vertex ai, the leading ai platform for bringing gemini models to enterprise customers.
responsibilities
lead an asic subsystem.
understand how it interacts with software and other asic subsystems to implement data center networks.
define hardware/software interfaces. write micro architecture and design specifications.
define efficient micro-architecture and block partitioning/interfaces and flows.
collaborate closely with software, verification, and physical design stakeholders to ensure the designs are complete, correct, and performant.

be part of a team that pushes boundaries, developing custom silicon solutions that power the future of direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
our mission is to organize the world's information and make it universally accessible and useful. our team combines the best of ai, software, and hardware to create radically helpful experiences. we research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. we aim to make people's lives better through technology.as a power and signal integrity engineer, you will be responsible for the design and characterization of signal and power integrity of our ic designs. you will design the external electrical interfaces of the device, from their signal/power-integrity and electrical usage perspectives.you'll set up methodologies, perform simulations, silicon characterization and correlations to ensure our ic designs meet systems design budgets and achieve the highest performance. you will work with systems architects, asic design, systems engineers, and partner cross-functionally with teams and external vendors/partners.the ml, systems, & cloud ai (msca) organization at designs, implements, and manages the hardware, software, Machine Learning, and systems infrastructure for all services (search, youtube, etc.) and cloud. our end users are, cloud customers and the billions of people who use services around the world. we prioritize security, efficiency, and reliability across everything we do - from developing our latest tpus to running a global network, while driving towards shaping the future of hyperscale computing. our global impact spans software and hardware, including clouds vertex ai, the leading ai platform for bringing gemini models to enterprise customers.
responsibilities
design and optimize power distribution networks (pdn) across chip, package, and board levels. this includes managing power/ground planes, decoupling capacitors, and power gating strategies.
conduct both pre-layout and post-layout power integrity simulations to analyze power and ground noise (ssn/sso), voltage drops (ir drop), and electromagnetic interference (emi).
implement and verify low-power design methodologies, such as multi-voltage designs and clock gating, using power intent formats like upf/cpf.
generate precise electrical models (e.g., s-parameters, spice models) for components such as packages, pcbs, and connectors for use in simulations.
execute lab measurements utilizing TEST equipment like oscilloscopes, vector network analyzers (vna), time domain reflectometers (tdr), spectrum analyzers to validate simulation outcomes and debug signal and power-related issues on silicon prototypes and boards.

as a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. you develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of google users.
as a cmos technologist and foundry engineer, you'll be part of the growing chip design team. in this role, you'll be responsible for driving cmos (complementary metal oxide semiconductor) foundry partners, intellectual property (ip), and chip design and implementation teams to perform cmos transistor scaling and power/performance analysis (ppa), and producing technology roadmap benchmarks. you will also be involved in interfacing and driving our design ip partners.the ai and infrastructure team is redefining whats possible. we empower google customers with breakthrough capabilities and insights by delivering ai and infrastructure at unparalleled scale, efficiency, reliability and velocity. our customers include googlers, google cloud customers, and billions of google users worldwide. we're the driving force behind google's groundbreaking innovations, empowering the development of our cutting-edge ai models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. from software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our tpus, vertex ai for google cloud, google global networking, data center operations, systems research, and much more.
responsibilities
engage with cmos foundry partners, manage foundry design kits and design library collaterals, and work with our design teams to perform ppa simulations on benchmark circuits.
work with fab partners on device and circuit level TEST structures, TEST chips, and characterization and correlation of silicon data. you will use the results of this work to influence design optimizations.
work with ip partners, design, and physical design teams to design advanced cmos.
work with chip implementation and physical design teams on micro-architecture tradeoffs, support design tool flow bring-up, and address all physical implementation details leading to product tapeout.
work with our commercial and product teams on foundry and ip vendor management, track technology roadmaps, and determine appropriate technology and ip integration strategies.

be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
with your technical expertise you will manage project priorities, deadlines, and deliverables. you will design, develop, TEST, deploy, maintain, and enhance software solutions.the ml, systems, & cloud ai (msca) organization at our designs, implements, and manages the hardware, software, Machine Learning, and systems infrastructure for all our services (search, youtube, etc.) and our cloud. our end users are  cloud customers and the billions of people who use our services around the world. we prioritize security, efficiency, and reliability across everything we do - from developing our latest tpus to running a global network, while driving towards shaping the future of hyperscale computing. our global impact spans software and hardware, including our clouds vertex ai, the leading ai platform for bringing gemini models to enterprise customers.
responsibilities
create software solutions that improve the hardware post-silicon testing process through automation. this includes, but is not limited to, developing and maintaining an automatic TEST equipment (ate) program development infrastructure for both production and development environments.
propose, design and implement software automation that directly addresses bottlenecks in today's post-silicon TEST flow, from design for testing (dft) to ate.
review code developed by other developers and provide feedback to ensure best practices (e.g., style guidelines, checking code in, accuracy, testability, and efficiency).
contribute to existing documentation or educational content and adapt content based on product/program updates and user feedback.
triage product or system issues and debug/track/resolve by analyzing the sources of issues and the impact on hardware, network, or service operations and quality.

we're the driving team behind groundbreaking innovations, empowering the development of our cutting-edge ai models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. from software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our tpus, vertex ai for google cloud, google global networking, data center operations, systems research, and much more.
responsibilities
define the block level design documents such as interface protocol, block diagram, transaction flow, pipeline, and more.
perform rtl development (e.g., coding and debug in verilog, systemverilog, vhsic hardware description language (vhdl)), function/performance simulation debug, and lint/cdc/fv/upf checks.
participate in synthesis, timing/power, and fpga/silicon bring-up.
participate in TEST plan and coverage analysis of the block and SOC -level verification.
communicate and work with multi-disciplined and multi-site teams.

be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.as a power and signal integrity engineer, you will be responsible for the design and characterization of signal and power integrity of our ic designs. you will design the external electrical interfaces of the device, from their signal/power-integrity and electrical usage perspectives and set up methodologies, perform simulations, silicon characterization and correlations to ensure our ic designs meet systems design budgets and achieve the highest performance. you will work with systems architects, asic design, systems engineers, and partner cross-functionally with teams and external vendors/partners.the ml, systems, and cloud ai (msca) organization at our designs, implements, and manages the hardware, software, Machine Learning, and systems infrastructure for all our services (search, youtube, etc.) and our cloud. our end users are cloud customers and the billions of people who use our services around the world. we prioritize security, efficiency, and reliability across everything we do - from developing our latest tpus to running a global network, while driving towards shaping the future of hyperscale computing. our global impact spans software and hardware, including our clouds vertex ai, the leading ai platform for bringing gemini models to enterprise customers.
responsibilities
generate precise electrical models (e.g., s-parameters, spice models) for components such as packages, pcbs, and connectors for use in simulations.
simulate high speed interface electrical behavior using hspice or other circuit simulators.
execute lab measurements utilizing TEST equipment like oscilloscopes, vector network analyzers (vna), time domain reflectometers (tdr), spectrum analyzers to validate simulation outcomes and debug signal and power-related issues on silicon prototypes and boards.
establish design rules and guidelines for optimal signal/power integrity during pcb and package layout, ensuring high production yield and reliability.
document design specifications, analysis results, and validation reports to ensure compliance with standards and for future reference, while collaborating extensively with cross-functional teams, including asic architects, digital/analog designers, physical design/layout engineers, and system engineers