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We are seeking for Platform Integration Engineer to own the development, testing, and monitoring of the manufacturing health of our Graviton server products. You will be part of a team integrating new silicon, hardware, firmware, and software into a revolutionary system architecture.

Key job responsibilities:
Lead product integration from definition phase through mass production, including: Hardware-Firmware integration and validation, development and implementation of manufacturing test flows, system validation and qualification and production readiness verification.
Define and implement screening test content for both production line and data-center environments.
Drive continuous improvement of operational health monitoring and debugging capabilities.
Collaborate with cross-functional teams to resolve integration and production issues.
Implement test flows for improving product operational health at manufacturing sites.
Integrate knowledge and data from customers and data sources for fast resolution of operational issues.
Maintain quality documentation and collateral in order to improve manufacturing operations.
Travel to manufacturing sites as needed (approximately 3-4 times per year, 1 week duration per trip) to support integration, validation, and operational improvements.

We are looking for excellent electrical engineering graduates to join our talented Chip Design group developing Amazons next generation products for the cloud market. This is a unique opportunity where you will be be able to learn from our technical experts and team leaders about architecture definition, logic design, verification, chip bring-up and more.
In this role you will impact and see the device through its entire lifecycle from definition stage to mass production and to our datacenters.

We are looking for an experienced engineer for the Nitro cards product team. Our products include the most advanced interfaces and technologies and widely used across our data centers as backbone for Nitro and other services. The candidate will serve as expert for Nitro HW power domain - ensuring best design, integration and operational health for power domain for our Nitro cards in our data centers.

As a member of a product team you will own complex system debugs involving HW, FW and SW components. You will deal with functional and integration aspects related to complex systems focusing on the power domain related to Nitro HW. You will be involved in architecture decisions, integrations, deployments and debugging related to complex systems while also providing remote and on-site support to our global colleagues.
You will also provide leadership by driving the teams around you to raise the bar and deliver higher quality product on behalf of our customers. This is a fast-paced, intellectually challenging position, and you will work with thought leaders in multiple areas of technology. You will set high standards for yourself and everyone you work with, and will be constantly looking for ways to improve the performance, quality, cost and reliability of products and services you own. We are changing an industry, and we want individuals who are ready for this challenge and want to reach beyond what is possible today.

Key job responsibilities:
- Lead triage, debug and root cause analysis of Nitro HW Power domain related issues in our systems (card / system level).
- Enhancing the ability to trouble shot issues and driving for closure of in-fleet problems.
- Analyze customers` mode of work / requirements and provide resolutions accordingly.
- Co-work with Annapurna Labs monitoring team and other root cause teams to improve quality and reliability of products operation in the fleet.
- Provide Annapurna Labs Board, ASIC and system design, SW and testing development, QA and architecture teams information and requirements from customers fleet operation perspectives and represent the customer voice.
- Drive and maintain trainings, quality documentation and collateral in order to improve in-fleet operation.
- Design and define various tools and scripts to provide support to projects and customize it as per requirement.
- Willing to travel per need few times a year.

We are looking for an Embedded Software Engineer to join the SW group and take a major part in redefining the future of our cloud.
Were searching for engineers with a passion for networking to develop SRD (Scalable Reliable Datagram). SRD is a high-performance, low-latency transport protocol used within us infrastructure to optimize network performance. SRD powers several high-impact products, including on-demand ML and HPC platforms leveraging EFA, next-generation storage services built on EBS, and the future of our network traffic.

As an Embedded Software Engineer on the SRD team, your primary responsibility will be to develop and optimize SRD technology across our network infrastructure. You will work on high-performance platforms that power ML, HPC, and storage-intensive workloads.
Your role will involve designing, deploying, and maintaining the SRD codebase, ensuring its reliability and scalability to meet the demands of diverse applications. You will gain in-depth knowledge of the various platforms and services running SRD within us, diving deep to understand their unique challenges and complexities.
Collaboration will be key, as you will work across multiple teams at different layers of the software stack. You will also contribute to defining new hardware modules and enabling offloads to enhance performance.

We are looking for an Embedded Software Engineer to join the SW group and take a major part in redefining the future of our cloud.
Were searching for engineers with a passion for networking to develop SRD (Scalable Reliable Datagram). SRD is a high-performance, low-latency transport protocol used within our Web Services infrastructure to optimize network performance. SRD powers several high-impact products, including on-demand ML and HPC platforms leveraging EFA, next-generation storage services built on EBS, and the future of our network traffic.

As a Senior Network Software Engineer on SRD team, your primary role will be to develop and optimize the implementation of SRD technology across our network infrastructure. Your responsibilities will encompass designing, deploying, and maintaining SRD code-base, ensuring its reliability and scalability to accommodate the demands of various applications. An essential part of your role will involve conducting extensive network simulations to evaluate system performance under different conditions, enabling you to identify potential bottlenecks and inefficiencies. Using these simulations, you will troubleshoot network issues and implement robust solutions, leading to minimal data loss and latency. Leveraging your in-depth understanding of network protocols and our infrastructure, you'll refine and improve the SRD system's performance. Furthermore, you will be expected to mentor junior team members, leading projects to advance the SRD capabilities within the environment. Staying updated with the latest industry trends and incorporating them into strategic network service planning.

About the job
our company's custom-designed machines make up one of the largest and most powerful computing infrastructures in the world. The Hardware Testing Engineering team ensures that this cutting-edge equipment is reliable. In the R&D lab, you design test equipment for prototypes of our machinery and develop the protocols used to scale these tests for the entire global team. Working closely with design engineers, you give input on designs to improve our hardware until you're sure it meets our company's standards of quality and reliability.
As a Chip Infrastructure Engineer, you will plan and execute work in an innovative and fast-paced environment, with a focus on infrastructure that enables design and verification teams to produce the chips that power our company's computing needs. You'll be part of the chip infrastructure team responsible for compute, storage, common chip design components, and front-end tool flows.
In this role, you will work with architects, logic designers, and verification engineers to develop flows to build and verify SoC chip designs. Youll also work closely with software, physical design, silicon bring-up and validation teams to enable a successful software integration, implementation, silicon bringup and deliver quality silicon.
The ML, Systems, & Cloud AI (MSCA) organization at our company's designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all our company's services (Search, YouTube, etc.) and our companys Cloud. Our end users are our companyrs, Cloud customers and the billions of people who use our company's services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including our company's Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Work with partner teams to provide the compute, storage and methodology needs of the chip design, verification and physical design teams.
Collaborate with Application-Specific Integrated Circuit (ASIC) teams to implement tools and methodologies.
Design and implement CAD tools, solutions and methodologies for ASIC development.
Extend the capabilities of third-party tools through their dedicated APIs.
Provide documentation, training, and support to increase end user productivity.

About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a System on a Chip (SoC) Design for Test (DFT) Engineer, you will be responsible for defining, implementing, and deploying advanced DFT methodologies for digital or mixed-signal chips. You will define silicon test strategies, DFT architecture, and create DFT specifications for next generation SoCs. You will design, insert, and verify the DFT logic and prepare for post silicon and co-work/debug with test engineers.
The ML, Systems, & Cloud AI (MSCA) organization at our company designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all our company services (Search, YouTube, etc.) and our company Cloud. Our end users are our companyrs, Cloud customers and the billions of people who use our company's services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including our company Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Develop DFT strategy and architecture (e.g., Memory Built-In Self Test (MBIST), Automatic Test Pattern Generation (ATPG), hierarchical DFT).
Complete all Test Design Rule Checks (TDRC) and design changes to fix TDRC violations to achieve high-test quality.
Insert DFT logic, boundary scan, scan chains, DFT Compression, Logic Built-In Self Test, Test Access Point (TAP) controller, clock control block, and other DFT IP blocks.
Insert and hook up MBIST logic including test collar around memories, MBIST controllers, eFuse logic, and connect to core and TAP interfaces.
Document DFT architecture, test sequences, and boot-up sequences associated with test pins.

About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As the DFT Senior Engineer, you will play a crucial role in DFT Architecture and DFT design, and support devices of extreme complexity to production. You will be responsible for providing technical leadership in DFT, developing flows, automation, and methodology, planning DFT activities, tracking the DFT quality matrix throughout the project lifecycle, and providing sign-off DFT to tapeout.
The ML, Systems, & Cloud AI (MSCA) organization at our company's designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all our company's services (Search, YouTube, etc.) and our company Cloud. Our end users are our companyrs, Cloud customers and the billions of people who use our company's services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including our company Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Lead and execute activities in the design, implementation, and verification of DFT solutions for large-scale Application-Specific Integrated Circuits (ASIC).
Develop DFT strategy and architecture, including hierarchical DFT, Memory Built-In Self Test (MBIST), and Automatic Test Pattern Generation (ATPG).
Work with other Engineering teams (e.g., Design, Verification, Physical Design) to ensure that DFT requirements are met and mutual dependencies are managed.
Manage the DFT team's workload and deliverables, provide technical leadership and guidance to the team.
Lead DFT execution of a silicon project - planning, execution, tracking, quality, and signoff.