לוח משרות דרושים מהנדסים בבאר שבע

We are looking for a Formal Verification Engineer for our company Networking team!
This is an exciting opportunity to join a hardworking Pre-Silicon design and verification team, working on groundbreaking NIC technologies. We deploy state-of-the art formal verification tools and methodologies to prove design correctness. Working in our formal verification team will expose you to a wide range of cutting edge design and technologies. Our NIC team delivers world class CPU interface and offload solutions for AI, HPC, data-center, network, and storage markets. We micro-architect, verify, and deliver the best and most widely used high BW ethernet and IB NICs in the industry. our company has the most sophisticated formal tools and methodologies in the industry, which help us achieve A0 design tapeouts. As part of this team, you'll enjoy a versatile work environment, which is educational, dynamic and ambitious.
What you'll be doing:
In this position you will use formal verification algorithms to formally prove the correctness of complicated logic problems.
You will work on ambitious designs along with our Pre-Silicon team and take part in developing the next generation of our company's core technology.

we are looking for a talented DevOps Engineer to join the data-center-on-a-chip (DOCA) Software group. As a part of the team, you will lead complicated integrations which combining new technologies, automating processes, bringing up full software stacks, developing system scripts for cutting edge networking technologies with the quality requirements of industry-leading customers. You will work closely with our company's SDK development and gain an understanding of our company's products and technologies.
What youll be doing:
Developing DevOps tools using various company proprietary and other cutting-edge technologies to help build better CI/CD workflows
Crafting efficiency and usability improvements across our company proprietary products that will help streamline various release pipelines and processes across our company
Creating and maintaining build system for complex SW products
Definition and development of SDKs to be used for DOCA SW development.

We are looking for an excellent Senior Firmware Verification Engineer to join the Firmware team. The company Firmware team develops groundbreaking networking features for AI, cloud, HPC and storage. We drive the data growth of the worlds biggest companies. With many hardworking engineers around the globe, the work environment is complex, results-oriented and fast paced. You will learn how a big software project is operated, maintained, qualified and released, and how Hardware and Firmware are developed
What you will be doing:
Work closely with the architecture and different software and hardware design teams.
Implement new features for our company NIC and Switch firmware.
Develop verification tests for advanced features in a highly complex and sophisticated Firmware testing environment.
Collaborate with multi-functional teams including chip design, board designers, Silicon, SW and program managers to debug any FW/validation issues.
Heavily involved with the early modeling and simulation required to produce our outstanding products including schematic and layout reviews on next generation board designs.

The complexity of the chip has greatly increased over the years. We are now packing tens of billions of transistors in a chip to meet the growing computing demand in a footprint that is responsible to our environment. The company System-On-Chip (SOC) group is looking for a top ASIC Engineer with a curiosity about SOC design automation, RTL integration, chip build and assembly, and padring design and verification. You should have real passion for methodologies and automation solutions that enable SOC creation in the most optimized way.
In this position, you will get the opportunity to build complex networking chips and interact directly with unit-level ASIC, Physical Design, CAD, Package Design, Software, DFT and other teams.
What you'll be doing:
Lead the end-to-end execution, tracking, and convergence of chip-level CDC and RDC for complex SoCs across all IPs and partitions.
Plan and orchestrate CDC/RDC signoff: define methodology, scopes, run plans, constraints, and acceptance criteria.
Run and maintain CDC/RDC flows and rule decks, including multi-mode, multi-clock, and hierarchical signoff.
Triage violations efficiently: root-cause to RTL, constraints, tool setup, or IP models; prioritize and drive fixes to closure with owners.
Verify reset architecture and RDC robustness (reset domain intent, release sequencing, glitch detection, fanout).
Author and review CDC/RDC constraints, waivers, and justifications; ensure auditability and signoff quality.
Automate runs, report parsing, dashboards, and KPIs for closure tracking using scripting and data tooling.
Partner with RTL, DV, DFT, STA, PD, and Architecture to align fixes, manage ECOs, and protect CDC/RDC quality during late design changes.
Define and enforce signoff gates; communicate progress and risks with clear metrics and issue tracking.
Continually improve methodology and training to prevent recurring CDC/RDC issues and accelerate convergence.

our company has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. Its a unique legacy of innovation thats fueled by great technologyand amazing people. Today, were tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing whats never been done before takes vision, innovation, and the worlds best talent. As a worker, youll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world.
The complexity of the chip has greatly increased over the years. We are now packing tens of billions of transistors in a chip to meet the growing computing demand in a footprint that is responsible to our environment. The our company System-On-Chip (SOC) group is looking for a top ASIC Engineer with a curiosity about SOC design automation, RTL integration, chip build and assembly and verification. You should have real passion for methodologies and automation solutions that enable SOC creation in the most optimized way. In this position, you will get the opportunity to build complex networking chips and interact directly with unit-level owners, Physical Design, CAD, Package Design, Software, DFT and other teams.
What you'll be doing:
Designing and implementing SOC level clock requirements
Developing and deploying automation flows which support SOC level design
Daily work involves aspects of chip level design, including partitioning, CDC, trial synthesis, design quality checks
Be exposed and work on a variety of functional and structural challenges. Including functional debug, physical design readiness, emulation, resolve design quality issues.

we are widely considered to be one of the technology worlds most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us and, due to unprecedented growth, our exclusive engineering teams are rapidly growing. If you're a creative and autonomous engineer with a real passion for technology, we want to hear from you.
we are looking for a phenomenal Senior Verification Engineer for HW Simulation for the ChipSim Group. You will join the ChipSim growing team and take our product to next level, working closely with HW design and architect teams and gaining a deep understanding of our companys products and technologies.
What Youll Be Doing:
Develop and maintain robust test environments, verification flows, and infrastructure.
Define and execute comprehensive test plans for existing and next-generation networking features.
Take ownership of functional, integration, and regression testingfrom planning through execution.
Build automated test suites and integrate them into CI pipelines to ensure quality at scale.
Collaborate across architecture, firmware, and HW teams to drive quality and early bug detection.
Analyze complex system behaviors and drive debugging efforts across hardware and software boundaries.

The complexity of the chip has greatly increased over the years. We are now packing tens of billions of transistors in a chip to meet the growing computing demand in a footprint that is responsible to our environment. The our company System-On-Chip (SOC) group is looking for a top ASIC Engineer with a curiosity about SOC design automation, RTL integration, chip build and assembly, and padring design and verification. You should have real passion for methodologies and automation solutions that enable SOC creation in the most optimized way.
In this position, you will get the opportunity to build complex networking chips and interact directly with unit-level ASIC, Physical Design, CAD, Package Design, Software, DFT and other teams.
What you'll be doing:
Implement chip level design through collaboration with cross-functional teams (Functional Design, DFT, Design Verification, System Verification, STA, and Physical Design).
Be exposed and work on a variety of functional and structural challenges. Including functional debug, physical design readiness, emulation, resolve design quality issues.
Daily work involves aspects of chip level design, including partitioning, CDC, RDC, trial synthesis, design quality checks
Taking part in flows development and deployment.

We are looking for a Formal Verification Engineer for our company Networking team!
This is an exciting opportunity to join a hardworking Pre-Silicon design and verification team, working on groundbreaking NIC technologies. We deploy state-of-the art formal verification tools and methodologies to prove design correctness. Working in our formal verification team will expose you to a wide range of cutting edge design and technologies. Our NIC team delivers world class CPU interface and offload solutions for HPC, data-center, network, and storage markets. We micro-architect, verify, and deliver the best and most widely used high BW ethernet and IB NICs in the industry. our company has the most sophisticated formal tools and methodologies in the industry, which help us achieve A0 design tapeouts. As part of this team, you'll enjoy a versatile work environment, which is educational, dynamic and ambitious.
What you'll be doing:
In this position you will use formal verification algorithms to formally prove the correctness of complicated logic problems.
You will work on ambitious designs along with our Pre-Silicon team and take part in developing the next generation of our company's core technology.
You will learn state of the art formal methodologies and advance your expertise in communication protocols and hardware implementations.

Are you passionate about working on a team that is at the cutting and bleeding edge of hardware technology? Our Design-for-Test Engineering team at our company works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most sophisticated semiconductor chips. We are looking for a DFT Engineer to join the ATPG team. The position includes taking part in development of the next generation DFT technologies and working closely with a wide range of our groups and aspects - chip design, backend, verification, and production testing.
Working on the most advanced technologies and complex products, our DFT solution are unique and innovative internal developments, and we are continuously improving and evolving the solution to meet the challenging goals. If you find groundbreaking Technologies, and next generation products interesting, then this is the team for you. Take opportunity to join our team for an exciting and educational environment, where every individual has significant contribution to our products and achievements!
What youll be doing:
You will be in charge of state of the art Design for Test/ATPG flows and implementation
Take ATPG ownership on different DFT aspects of a project, Arch & planning, pattern generation, verification and post Silicon bring up and diagnosis.
Inventing and maintaining automation flows that provide the short test time to production.

we are seeking a technical leader interested in defining, crafting, implementing, and guiding the implementation of security research, architecture, implementation, and design for next-generation our company Networking products. You'll be expected to take a strong hands-on role, working with diverse teams across our company and with external partners to meet security requirements for our state-of-the-art network products.
our companys invention of the GPU 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI the next era of computing with the GPU acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. Today, we are increasingly known as the AI computing company. We are looking to grow our teams with the smartest people in the world. If you're creative and autonomous, we want to hear from you!
What you'll be doing:
Research, design, develop and implement architecture solutions (Hardware and software) meeting internal and external security requirements and standards.
Apply innovative hardware security primitives to enable next generation secure software extensions supported by hardware.
Design next generation production and provisioning systems.
Collaborate with partners on the implementation of open-source software.
Collaborate across the company to guide the direction of Its (USB, I2C, I3C, UART, PCI) working with hardware, software, research and product teams.
Architectural modeling, validation, microarchitectural definition, following standards bodies, and developing infrastructure enabling trusted platforms using hardware security methods.
Work with customers, partners to identify and address security issues and threats.

we are looking for a Senior Chip-Design Verification Engineer to join our Network Adapter Silicon group. As a Senior Verification Engineer at our company Networking Silicon team, you will join a group of passionate engineers to design and implement the next generation state-of-the-art Networking Silicon chips. In this position, you will make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!
What you'll be doing:
Work in a combined design and verification team which develops core units within the Networking silicon.
Build reference models, verify and simulate chip blocks/entities according to specifications and performance requirements.
Work closely with multiple teams within organizations such as Architecture, Micro- Architecture, FW and Post-Silicon validation.

we are looking for best-in-class Chip Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! Come and take a significant part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a huge impact in a technology-focused company.
What you will be doing:
Join Beer-Sheva group, working on RiscV processors platform.
Lead a team of engineers responsible for the functional verification of complex silicon chips, ensuring the designs meet all functional, performance, power, and quality requirements before production. This role involves strategic planning, hands-on technical leadership, cross-team collaboration, and process improvement within the chip development lifecycle.
Define verification methodologies and strategies, ensuring comprehensive coverage of functional, performance, and power requirements.
Plan and manage verification projects, including scheduling, resource allocation, and progress tracking to meet project milestones.