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As a Solution Engineer for Next-Gen Trust Security (NGTS), you are the premier technical subject matter expert for Palo Alto Networks' Machine Identity Management portfolio. Following our integration with our company, you will lead the technical charge in transforming how enterprises manage cryptographic trust.
You will be responsible for defining technical solutions that secure critical business imperatives, evangelizing our "better together" integration of Certificate Lifecycle Management (CLM) and Zero-Touch Public Key Infrastructure (ZTPKI) within the Strata Cloud Manager (SCM) platform. You will serve as the technical bridge between the Network Security teams and Identity stakeholders, ensuring that enforcement systems (NGFW/SASE) stay synchronized as certificate lifecycles compress.
Your Impact
Technical Win Leadership: Lead Proof of Value (PoV) engagements and technical validations for NGTS, ensuring a high technical win rate by demonstrating operational resilience and outage elimination.
Solution Architecture: Design unified cryptographic governance models within Strata Cloud Manager that align certificate operations with network enforcement.
Strategic Execution: Identify critical projects and actions required to achieve a customer's desired security end-state; eliminate sales obstacles through creative and adaptive problem-solving.
Market Evangelism: Act as a thought leader on the "Cryptographic Reset," educating CISOs and VP-level stakeholders on the risks of 47-day certificate lifecycles and the path to Post-Quantum Cryptography (PQC).
Product Advocacy: Share industry experience regarding customer usage patterns to provide feedback to product teams on how to make NGTS/MIM easier for customers to adopt fully.
Strategic Discovery: Conduct deep-dive discovery sessions to uncover unmanaged or "rogue" certificates using network-native discovery tools.
Cross-Functional Collaboration: Partner with Solutions Consultants (SCs), Account Managers, and the company MIM Specialist team to build and execute account-based pursuit strategies.
Platformization: Drive the adoption of Secure Flex credits by showing customers how to consolidate siloed CLM/PKI tools into a centralized control plane.

As part of your role, you will design, implement, and deploy products and infrastructures that will directly increase our stability and quality while reducing our time to market. You will have end-to-end ownership from individual development environments and SCM/Build/CI servers to our production system on AWS.
Your Impact:
Design and manage Continuous Integration/Deployment Services, including build, packaging, and deployment.
Design, document, implement, and maintain scripts to enhance current and future build and release processes.
Incorporate new development projects into existing build structures.
Continually evaluate tools and technologies to improve the overall release process.

As a QA Engineer , you will play a key role in validating and improving our products, ensuring high quality.
You will join RADs family, as part of our team in Beer-Sheva, collaborating closely with software development teams in an agile and dynamic environment.

Location: Beer Sheva. Hybrid option once a week.

Responsibilities
Design and execute test plans and test cases based on system requirements
Identify, investigate, and report software bugs, while tracking them through resolution
Create and maintain clear test ation and reports
Collaborate with R&D teams to provide QA input throughout the development lifecycle
Communicate risks and quality concerns that may impact future releases

We are building the software foundation for the next generation of AI infrastructure. As AI workloads continue to evolve, Kubernetes and the cloud-native ecosystem must evolve with them.

Our teams mission is to make Kubernetes the best platform for AI workloads. We work upstream with the Kubernetes and CNCF communities to design new APIs, build production-grade implementations, and shape the future of cloud-native infrastructure for AI.

As a Senior Software Engineer, you'll tackle the most challenging problems at the intersection of Kubernetes, distributed systems, and AI infrastructure.


What you'll be doing:

Design, implement, and upstream new capabilities for Kubernetes and CNCF projects.

Collaborate with engineering teams across us to identify AI infrastructure challenges and solve them through upstream innovation.

Work closely with Kubernetes SIGs, Working Groups, and the broader open-source community to design and implement new capabilities.

Participate in architecture discussions, API design, technical proposals, and code reviews.

Build reliable, scalable infrastructure software for next-generation AI workloads.

Write clear technical documentation and design proposals.

We are looking for best-in-class Chip Design Verification Engineer to join our outstanding Networking Silicon engineering team. We are developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! Come and take a significant part in designing and verifying our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a huge impact in a technology-focused company.

What you will be doing:

Join accelerators IP group in Beer-Sheva, working on RiscV processor IPs.

Verification for chip blocks according to specifications under challenging constraints and with high orientation to power, area and performance.

Daily work might involve any or all aspects of chip development: Verification, Design.

Work closely with Firmware and other groups around the globe.

We are seeking a Front-End Integration Engineer for the NIC Silicon group. Join our team in our Networking business unit and be part of the innovative build and implementation of the next generation Network Adapter Silicon chips. Contribute to the development of powerful communication devices.

What You'll Be Doing:

Own and maintain Continuous Integration pipelines. Monitor, complete, and fix daily and nightly CI flows in front-end build areas. These include Lint, Synthesis, Equivalence Checking and Simulation.

Automate EDA Flows: Build, develop, and maintain robust automation scripts using Python, Tcl scripting, and Shell to integrate EDA tools (Synopsys, Cadence) into automated build pipelines.

Manage Perforce Integration: Maintain multi-IP branch/stream strategies, manage workspace specs, complete hardware build drops, and handle release labels/tags in Perforce (Helix Core).

Support Engineering Teams: Act as the primary point of contact for RTL and verification engineers to debug flow crashes, bottlenecks, environment setups, and CI failure reports.

Enforce Quality Gates: Implement automated check-in and change list triggers to run sanity checks, linting, and style enforcement before code is committed to main streams.

Optimize Infrastructure: Monitor compute farm resources (LSF) and storage usage to reduce pipeline runtime and improve overall execution efficiency.

The System-On-Chip (SOC) group is looking for a strong RTL Design Engineer to own the SOC clocking logic for our next-generation networking chips. Clocks are the backbone of the SOC. In this role you will own the clock generation, distribution, and control logic for the entire chip - PLL and reference clock integration, clock muxing and dividers, glitchless switching, clock gating, reset synchronization, and the clock domain crossing infrastructure that every unit on the die depends on.

This is an RTL design role, not a circuit or transistor-level design role. You will translate micro-architecture specifications into high-quality synthesizable RTL, and drive that RTL through to silicon in close partnership with the micro-architecture, Design Verification, and Physical Design (backend) teams. You will also interact with CAD, Package Design, Software, and DFT teams.

What you'll be doing:

Owning the SOC clocking logic end to end: writing synthesizable Verilog/SystemVerilog RTL for clock generation, distribution, muxing, division, glitchless switching, gating, and reset synchronization, from micro-architecture specification through tape-out.

Defining and implementing the SOC clock and reset architecture together with the micro-architecture team - collecting clocking requirements from every unit on the chip and turning them into a coherent, verifiable design.

Owning clock domain crossing infrastructure and CDC closure across the SOC.

Partnering with the micro-architecture team to review specifications, close on design intent, and provide feedback on implementation cost, timing, area, and power.

Working hand-in-hand with the Physical Design (backend) team on clock tree implementation and constraints, partitioning, floorplan and timing feedback, trial synthesis, congestion and timing convergence, and physical design readiness.

Supporting Software and firmware teams on clock programming sequences, DVFS, and low-power/clock-shutdown flows.

Driving design quality: lint, CDC/RDC, formal checks, synthesis QoR, connectivity and structural checks.

Supporting SOC-level chip build and assembly, and developing/deploying automation flows that make RTL integration and design quality checking repeatable and scalable.

Supporting emulation, firmware, and post-silicon bring-up customers of your design.

We are looking for an outstanding Senior Networking Software Architect to join the NIC/DPU Software and Firmware Architecture group. In this role, you will help define the next generation of our datacenter and AI networking platforms, with focus on DPU management, QoS, performance, telemetry, and software architecture across stacks. You will work closely with hardware designers, firmware/kernel driver teams, system engineers, validation, product management and customers. The role spans early architecture definition, pre-silicon design, bring-up, and production readiness for large-scale AI and cloud datacenter deployments.

What Youll Be Doing:

Own software and system architecture for next-generation DPU management, QoS, performance, telemetry, and observability features.

Define end-to-end control and management flows across DOCA, host drivers, embedded firmware, BMC, management controllers and external management systems.

Specify telemetry and observability requirements, including counters, logs, traces, events, health monitoring, debug data, and streaming telemetry.

Define management interfaces and APIs for configuration, provisioning, lifecycle operations, diagnostics, and field serviceability.

Write clear architecture specifications, interface definitions, flow diagrams, and design documents for software, firmware, and system teams.

Partner with R&D teams to translate high-level architecture into implementable designs and guide features through development, validation, silicon bring-up, and production.

Analyze system performance bottlenecks, interoperability issues, telemetry gaps, and customer-reported issues, then feed learnings into future architecture.

Collaborate with system and cluster architects to ensure NIC/DPU features fit end-to-end AI datacenter and cloud networking designs.