דרושים » חשמל ואלקטרוניקה » Semiconductor Quality & Reliability Engineer

Required Integration and Validation Architect
About the team:
Join our hardware systems team to drive DV/PV software readiness for our AV-HW Tier 1 products. Youll combine customer-facing technical leadership, detailed validation design and hands-on integration to secure internal acceptance and customer satisfaction with testability and coverage.
What will your job look like:
Youll lead customer technical reviews, present readiness and validation evidence, and resolve concerns about testability and coverage.
Youll translate customer expectations and system requirements into detailed integration plans, coverage, loads, diagnostics and monitoring requirements.
Youll define interfaces between DV/PV software, SoCs, test hosts, equipment and automation, guiding teams and suppliers through implementation and verification.
Youll bring up test setups, integrate hardware and software releases, and troubleshoot issues using measurements, logs and controlled experiments.
Youll use technical judgment to coordinate investigations and corrective actions across teams, and verify that issues are resolved.
Youll own technical documentation and customer review material, keeping coverage tables, procedures and reports aligned with demonstrated capabilities.
Youll accept or withhold technical readiness against agreed requirements and assess the validation impact of hardware and software changes.

A leading provider of advanced inertial navigation systems for defense and international markets, is looking for a Technical Manager for Space Programs to lead and execute technical management and system engineering activities for our multi‑discipline Fiber‑Optic Gyroscope (FOG) products developed for Space Applications.
This role ensures that system‑level requirements, architecture, integration, and verification processes are rigorously defined, implemented, and maintained throughout the product lifecycle.
In this role you will -
Develop and maintain system architecture, ensuring alignment with mission needs, environmental constraints, and product performance goals.
Define, document, and manage system requirements, including flow‑down to multidisciplinary engineering teams and full traceability
Serve as the technical focal point for optics, electronics, mechanics, firmware, and algorithms teams, ensuring cohesive system performance, system verification and product compliance to Space segment.
Identify system‑level risks, support mitigation planning, and ensure compliance with relevant space standards and reliability requirements.
Participate in technical reviews, support customer discussions, and provide system‑level documentation and reporting.
Prepare and maintain system specifications, ICDs, verification matrices, and engineering reports.
Reporting to Head of Space programs.
Full Time. Jerusalem

Required IC Package Layout Engineer
About the team:
We develop purpose-built hardware and AI technologies that power advanced driver-assistance and autonomous-driving solutions. Our EyeQ SoCs and imaging radar technologies are designed to deliver scalable, automotive-grade performance and help enable safer mobility worldwide.
Join our advanced packaging team and take ownership of package-substrate layout for cutting-edge digital and RF products. You will collaborate with silicon, package, SI/PI, PCB, manufacturing, and OSAT teams to deliver high-quality, manufacturable package layouts that meet demanding automotive requirements
What will your job look like:
Own IC package-substrate layout from feasibility through manufacturing release.
Perform die placement, bump fan-out, ball-map planning, package-size estimation, and layer planning.
Set up stack-ups, padstacks, design rules, and layout constraints.
Implement high-density bump-to-ball routing for signal, power, and ground nets.
Route high-speed and RF interfaces according to defined SI/PI constraints.
Perform DRC, connectivity, LVS/netlist, and DFM checks.
Generate artwork, fabrication drawings, reports, and release documentation.
Resolve layout-related queries from substrate manufacturers and OSATs.

As a member of our Physical Design group, you will take an integral part in bringing large scale SoCs to life, helping us deliver the next generation of our ground-breaking products.
You will own the physical design cycle at the partition/IP/Chip levels, including netlist to GDS implementation and verification.
Are you ready to join some of the world's leading engineers and work with state of the art design flows and process technology?
If you possess the knowledge and experience in any of the physical design domains and practices with track record of tape-outs in sub-micron technology, come join our group!

As a member of our Physical Design team in this highly visible role, you will directly own implementation and verification of design partition(s) / IPs (netlist to delivery of our final GDS) for a highly complex SoC utilizing state of the art process technology.
* Implementation - Block level PnR, floor-planning, clock, power planning and distribution.
* Verification and Analysis - Static Timing closure using commercial tools, Physical Verification as well as Electrical/Power Analysis (EM / IR-Drop / Xtalk / noise )

As a member of our Physical Design group, you will take an integral part in bringing large scale SoCs to life, helping us deliver the next generation of our ground-breaking products.
You will own the physical design cycle at the partition/IP/Chip levels, including netlist to GDS implementation and verification.
Are you ready to join some of the world's leading engineers and work with state of the art design flows and process technology?
If you possess the knowledge and experience in any of the physical design domains and practices with track record of tape-outs in sub-micron technology, come join our group!


As a member of our Physical Design team in this highly visible role, you will directly own implementation and verification of design partition(s) / IPs (netlist to delivery of our final GDS) for a highly complex SoC utilizing state of the art process technology.
* Implementation - Block level PnR, floor-planning, clock, power planning and distribution.
* Verification and Analysis - Static Timing closure using commercial tools, Physical Verification as well as Electrical/Power Analysis (EM / IR-Drop / Xtalk / noise ).

As member of the DV CAD team, you have the opportunity to impact our engineers who develop next generation of our products!
You will be responsible for developing software solutions used by thousands of DV engineers globally. You will be supporting design process of all chip families we make (iPhone, iPad, Mac, our Watch and more), and your work will help streamline this complex process. This role combines DV knowledge alongside modern software engineering practices. Your work will be very diverse, and you will have broad impact contributing to the success of us.


You will develop and drive software development of multiple tools across the DV space, including cloud-native services, GUI, LLM harness, CI/CD. Your work will span from software development and architecture to collaborating with DV engineers, working with EDA vendors, and supporting critical project milestones.

Responsibilities
Developing and maintaining LLM harness for agentic DV workflows, and being responsible for benchmarking and improving accuracy of agentic workflows.
Building and managing cloud-native services running on k8s, including CI/CD, containerization, alerting, databases, GUI and monitoring.
Communication with DV stakeholders and working to understand user requirements.
Writing and maintaining Python scripts used as part of design simulation flows.
Supporting multiple projects simultaneously.

As a manager in the RTL/FE CAD team, you have the opportunity to shape the future of chip design and impact our engineers who develop the next generation of our products! You will lead a high-impact team that develops software solutions used by thousands of RTL design and integration engineers globally across all chip families (iPhone, iPad, Mac, Apple Watch, and more).
In this role, you will be a key catalyst in transforming front-end hardware design into a modern, agile discipline. You will spearhead the transition to agentic workflows-redefining how RTL and integration teams operate in the AI era. This role combines deep knowledge of RTL/FE flows with modern software engineering practices, people leadership, and a transformative vision for engineering methodology.

Responsibilities
People Leadership: Lead, mentor, and grow a team of ~20 CAD engineers, driving talent acquisition, technical mentorship, performance management, and career development.
Agentic Flow & Methodology Transformation: Drive the team and broader RTL/FE community toward agentic workflows. Act as an organizational change agent, pioneering modern, agile methodologies that transform daily design and integration practices.
LLM Harness & Agentic Tooling: Own the architecture and execution of the LLM harness for RTL/FE flows (e.g., autonomous violation triage for Lint/CDC/RDC, intelligent connectivity synthesis, and design assist agents). Establish rigorous benchmarks to continually evaluate and elevate workflow accuracy and autonomy.
RTL Integration & Connectivity Tooling: Own end-to-end RTL integration tools, including connectivity generation, SoC assembly automation, IP packaging, and structural checks.
Static Sign-off Checks: Drive methodology, deployment, waiver governance, and sign-off metrics for Lint, CDC, RDC, and related static verification domains.
Roadmap & Milestone Alignment: Define strategic roadmaps and near-term execution plans aligned with multi-project tapeout milestones and long-term organizational goals.
Stakeholder & EDA Vendor Partnership: Collaborate closely with RTL design and integration leads to turn evolving design challenges into robust software solutions. Partner with EDA vendors to resolve escalations and influence tool roadmaps.
Software Excellence: Champion software engineering best practices, modern Python development, scalable cloud architectures, and robust CI/CD infrastructure within CAD.