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looking for a highly motivated Hardware Engineer to lead change impact analysis activities related to engineering design changes (ecos/ecrs) across our cutting-edge networking and computing platforms. this role is critical to ensuring that all product modifications are seamlessly evaluated for their impact on hardware, mechanical design, system performance, and TEST coverage across the product lifecycle. you will work closely with r&d, mechanical engineering, manufacturing, quality, and TEST teams to assess risks, define mitigations, and maintain excellence in product integrity and testability.
what youll be doing:
leading engineering change analysis (eco/ecr) processes across complex hardware systems.
evaluating the impact of component, layout, and mechanical changes on hardware functionality, manufacturability, and testability.
collaborating with cross-functional teams to ensure smooth implementation of changes without compromising product quality.
supporting dft (design for testability) requirements in the face of ongoing design changes.
reviewing bom and layout revisions and assessing ripple effects on power delivery, signal integrity, and thermal performance.
maintaining change traceability and documentation to meet engineering and compliance standards.
coordinating with manufacturing and operations teams to ensure product readiness and alignment with production timelines.

seeking a hardware & system development manager to join our system product engineering organization. in this role, youll own the creation and optimization of advanced TEST and validation platforms for nvidias high-performance networking products. these platforms power both r&d-level validation and mass production testing, ensuring exceptional product quality, reliability, and scalability.
at nvidia, we push the boundaries of whats possible in computing and networking. we believe that innovation thrives in an environment of teamwork, ownership, and technical excellence. we value ambitious thinking, thorough execution, and a shared commitment to creating exceptional products.
were looking for a board design leader with deep technical expertise and a passion for leading teams, driving end-to-end solutions, and fostering multidisciplinary collaboration. join us and be part of a team thats shaping the future of networking technologies!
what youll be doing:
lead the development of TEST hardware platforms, including customized TEST boards and system -level infrastructure.
own the full hardware lifecycle - from definition and schematic design to bring-up and production deployment.
deliver hardware used across r&d and manufacturing for functional, performance, and reliability testing.
collaborate with mechanics, signal integrity, layout, dft, firmware, and production teams to achieve seamless integration.
drive technical execution, project schedules, and cross-site coordination with precision and clarity.

looking for an excellent senior system Validation engineer!
networking division is a leading supplier of innovative end-to-end infiniband and ethernet connectivity solutions and services for servers and Storage. we offer market-leading solutions that include adapter cards, switches, cables, and software to support networking technologies. our products optimize data center performance and deliver industry-leading bandwidth and scalability. in addition, we serve a wide range of markets including high-performance computing, enterprise, data centers, cloud computing, Big Data, and web 2.0. we are constantly reinventing ourselves to stay ahead of the market and bring groundbreaking products and services to the industry.
what you'll be doing:
TEST verification and validation (both hw and sw).
maintain products quality by improving TEST stability, coverage, design, and manufacturing process in mass production.
execute tests in different scopes such: as regression, performance degradation, functional, and security; report the progress of testing and provide summary reports of the activity.
troubleshooting and streamlining/optimizing our testing procedures.
support mass production matters.
debugging production bugs and solving them.

our networking product engineering team is looking for an excellent TEST development engineer. the position requires an understanding of both hw and sw to provide stable, efficient, and smoothly running production tests that enable high availability while ensuring the quality of the products being shipped to customers.
what youll be doing:
design and develop automated tests for networking switches and dpu adapters while working closely with the hw, asic, and sw engineering teams to achieve reliable tests with high coverage.
be exposed to various aspects of design, dft, and TEST of nvidia's next-generation network products.
take a significant part in the definition and development of tests, from early development level to the final TEST of network-systems in mass production.
work with overseas manufacturing mass production teams to increase yields, TEST coverage and capacity, and to reduce production costs.
lead TEST solution innovations to reduce TEST time and improve overall product quality.
utilize TEST suites to find, debug, and resolve problems in the production process, and drive issues to closure.
support and fix bugs in existing TEST code; support production lines for deployments, patches, and ongoing maintenance.

testing electro-optical and electrical chips and systems.
link-level performance characterization, verification, and debugging.
responsibility for complicated setups establishments, covering both optical and electrical components
characterizing optical and electrical performance using lab equipment and sw tools.
take an active part in silicon bring-up while managing e2e testing of the newest asics, with the objective of driving product to mass production with first-in-class performance.
characterizing products performance using lab equipment, such as oscilloscope, spectrum/network analyzer, pattern-generator, etc.
working in front of various TEST teams, with the responsibility of addressing issues and monitoring the TEST flows conducted by them

the manager will be leading various type of reliability testings of nvidia ics, and responsible on nvidia reliability labs, which is a multi-millions $ worth of equipment as well as activities such as iqc, oqc, ic inventory managing and shipments.
this will include ate (automated TEST equipment), systems & evaluation boards and reliability equipment.
full management a team of technicians and operators, including day to day management, prioritization, focal reviews, and training.
maintaining and operating laboratory equipment such as ic ate, htol systems, scopes, dvms and other tooling, minimizing down time for all.
providing excellent support to engineers and our internal customers, carrying out q&r tasks and following strict execution methodologies.
establishing/maintaining a comprehensive engineering lab stock, apply skills to automate complex tasks and improve team productivity and efficiency.
entering and maintaining a database of work procedures and TEST data and reading schematics of electronic circuits.
building, updating, and improving lab processes and procedures while following and ensuring strict safety procedures and safety checks.

join our advanced packaging team to define and develop cutting-edge semiconductor package solutions for automotive-grade digital and RF system -on-chip ( SOC ) products.
youll collaborate with internal teams and external osats to deliver high-performance, manufacturable, and reliable packages that meet stringent automotive standards.
what will your job look like:
define and specify advanced package architectures for digital socs and RF ics in automotive applications.
perform substrate design for flip-chip bga (fc-bga) packages, including stack-up, routing, and ball-out optimizations.
evaluate and select substrate technologies, materials, and package solutions based on performance, cost, and reliability.
collaborate with osats to define and validate assembly materials and process flows.
work closely with internal teams such as backend, sipi, product engineering, and quality & reliability to ensure seamless integration.
monitor yield, quality, and manufacturability across package development and production stages.
support dfm reviews and ensure compliance with automotive standards and customer requirements.

as a quality and reliability (q&r) engineer, you will lead the qualification and long-term reliability of advanced system -on-chip ( SOC ) and RF semiconductor products for automotive applications. youll work across digital and RF domains to ensure robust performance and compliance with industry standards.
what will your job look like:
define and manage quality and reliability specifications, simulations, and qualification plans for SOC and RF die and package.
plan and execute automotive-grade qualifications per standards such as aec-q100, jedec jesd22, and iatf 16949.
design and implement die-level and package-level stress tests.
select and prepare electrical, environmental, and mechanical TEST platforms for reliability testing.
define requirements for pre-si q&r (e.g. esd, lu, em, ir drop), design-for- TEST (dft), electrical characterization, and post-si q&r testing of digital, mixed-signal and RF socs.
collaborate extensively with internal design teams, external subcontractors, and outsourcing partners (osats).
lead failure analysis, reliability modeling, and corrective action processes (e.g., 8d, fmea, fmeda).
document and certify automotive standards compliance, including ppap/apqp deliverables.

we are the production TEST team - responsible for the definition, development, and deployment of production TEST operations for the worlds most advanced socs for adas and self-driving vehicles.
this is your opportunity to join a team during its initial forming stage and leave your mark as our company assumes full ownership for its silicon production operations to enable high volume manufacturing for cutting-edge automotive products. what will your job look like?
work closely with the design teams from early stages of the design process to review dfx architecture and define TEST requirements.
define TEST methodologies and generate TEST content for high-speed interfaces of Embedded ip blocks (lpddr4/5, pcie gen4/5, d/ C /mphy).
TEST program coding, pattern conversion and pre-si validation (virtual TEST simulations)
support load board and probe card design activities.
lead post-si TEST program debug activities to enable delivery of samples to internal and external customers.
TEST program characterization and tuning to enhance TEST program quality to meet automotive standards.
support quality & reliability team to enable effective and timely qual plan execution.
lead TEST deployment activities with tier-one foundry and osat vendors to enable large-scale wafer-sort and final- TEST operations.

join our advanced packaging team to define and develop cutting-edge semiconductor package solutions for automotive-grade digital and RF system -on-chip ( SOC ) products.
youll collaborate with internal teams and external osats to deliver high-performance, manufacturable, and reliable packages that meet stringent automotive standards.
what will your job look like:
define and specify advanced package architectures for digital socs and RF ics in automotive applications.
perform substrate design for flip-chip bga (fc-bga) packages, including stack-up, routing, and ball-out optimizations.
evaluate and select substrate technologies, materials, and package solutions based on performance, cost, and reliability.
collaborate with osats to define and validate assembly materials and process flows.
work closely with internal teams such as backend, sipi, product engineering, and quality & reliability to ensure seamless integration.
monitor yield, quality, and manufacturability across package development and production stages.
support dfm reviews and ensure compliance with automotive standards and customer requirements.

as a quality and reliability (q&r) engineer, you will lead the qualification and long-term reliability of advanced system -on-chip ( SOC ) and RF semiconductor products for automotive applications. youll work across digital and RF domains to ensure robust performance and compliance with industry standards. what will your job look like:
define and manage quality and reliability specifications, simulations, and qualification plans for SOC and RF die and package.
plan and execute automotive-grade qualifications per standards such as aec-q100, jedec jesd22, and iatf 16949.
design and implement die-level and package-level stress tests.
select and prepare electrical, environmental, and mechanical TEST platforms for reliability testing.
define requirements for pre-si q&r (e.g. esd, lu, em, ir drop), design-for- TEST (dft), electrical characterization, and post-si q&r testing of digital, mixed-signal and RF socs.
collaborate extensively with internal design teams, external subcontractors, and outsourcing partners (osats).
lead failure analysis, reliability modeling, and corrective action processes (e.g., 8d, fmea, fmeda).
document and certify automotive standards compliance, including ppap/apqp deliverables.

we are looking for a senior pcb design layout engineer to join our hardware engineering team at the autonomous vehicle platform department as a key player in the development of next-generation ecu (electrical control unit) for autonomous vehicles. what will your job look like?
working closely with hardware and mechanical design engineers, you'll perform pcb layout our ecus and other products.
complete development of cad layout from footprint definition, detailed component placement, constraints management, with a concept of topology and signal and power integrity.
be responsible for the design releases required generation of artwork files, odb++, fab drawings, ict report, and electronic pcb documentation.
your designs will need to follow ipc class 3, signal and power integrity constraints, emi/rfi control and automotive regulations.

mentor new team members and enable existing team members to thrive.
support new ai fabric technologies based on nvidia networking solutions.
gain our customers trust, understand their needs, and translate them into technical actions and priorities.
work closely with multiple r&d teams from broad disciplines.
drive cooperation and alignment between ae, r&d, sales, business, and operations.
solve complex, highly visible customer issues across hw, fw, system and lead them to closure.
provide clear, constructive feedback to engineering and product/marketing on product requirements and quality.
own and improve methodologies, best practices, and debug flows used across the team.

architect end-to-end system validation strategies for new hardware platforms.
define TEST coverage and validation methodologies.
collaborate with hardware, software, qual and QA teams to align on product requirements and TEST coverage plans.
lead development of automation frameworks and diagnostics tools to enable scalable and repeatable testing.
analyze TEST data to identify root causes, guide debug efforts, and improve validation coverage.
provide technical leadership and mentorship across multidisciplinary teams and represent system TEST considerations in architecture and design reviews.

leading the development of groundbreaking microelectronics packaging for networking business unit's future products
collaborating with world-leading vendors to develop highly ambitious packaging solutions
thriving in a dynamic and challenging environment