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our company has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. Its a unique legacy of innovation thats fueled by great technologyand amazing people. Today, were tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing whats never been done before takes vision, innovation, and the worlds best talent. As a worker, youll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world.
At our company Networking, we are driven by innovation and excellence. Our team in Israel is looking for a dedicated Chiplet STA owner to join us in defining the next era of AI's networking. This is an outstanding opportunity to work with innovative technology and collaborate with some of the most experienced minds in the industry. If you are ambitious, passionate about flawless design, and eager to make a lasting impact, this role is perfect for you!
What you'll be doing:
Perform advanced Static Timing Analysis (STA) for HSIO at chiplet and FC level.
Running Prime Time, review and debug timing paths, understand constraints, sdc generation, timing ecos generation.
Identify convergence risks and work closely with physical design, RTL and DFT teams, ensuring convergence throughout various project stages.
Responsible for a full timing closer and quality approval from pre-layout STA model through signoff.

Innoviz Technologies is looking for a highly experienced and motivated VLSI Manager to lead the development of our next-generation ASIC—from initial concept to final production. In this pivotal role, you'll manage the entire ASIC development lifecycle, working closely with cross-functional teams and external partners to deliver cutting-edge technology that powers the future of autonomous vehicles. Responsibilities
* Own and lead the end-to-end ASIC development process.
* Act as the central point of contact for all ASIC-related activities, collaborating with Product, Firmware, Computer Vision, Hardware, and other stakeholders.
* Drive the ASIC program work plan, ensuring alignment and coordination across global teams and multiple workstreams.
* Define and enforce VLSI development methodologies, design flows, and quality standards.
* Evaluate and select both digital and analog IPs required for the ASIC.
* Manage relationships and deliverables with external VLSI partners and service providers, ensuring high-quality outcomes.

Sub Department:
VLSI

City:
Rosh Ha‘Ayin

We are looking for a creative and motivated HW development engineer with excellent problem solving and communication skills.
The HW development engineers responsibilities include designing and integrating analog and digital blocks in the flagship product.
The HW development engineer will report to the HW manager.
Job Responsibilities:
Design and integration of analog circuits including magnetics and communication filters
Board designing with emphasis on Power circuit
Design with ENC/EMI considerations
Board simulations
Layout, BOM, and DFM knowledge
Design power converters: DC-DC, AC-DC, AC-AC
Magnetics analysis using magnetic measuring tools and validation of theoretical results
Close work with embedded FW team

We Are Looking for a Creative and Motivated Real-Time Embedded Engineer With Excellent Problem-Solving Skills for Our Firmware Development Group
In this role, you will design and develop real-time embedded software for next-generation wireless power products.
Job Responsibilities:
Design, Develop, improve, and manage real-time embedded software from concept to final products.
Code architecture design and development over ARM Cortex-M & STM-8 microprocessors.
Integration of the real-time embedded software with external Hardware componets and products

we are Looking for a Creative & Motivated Product Manager
we are looking for a creative, experienced product manager to lead the companys strategic products in the fields of automotive, robotics, and telecom. we design and develops wireless power platforms (reference designs) which are integrated by leading OEMs, tier suppliers, ODMs, and semiconductors companies.
The Product Management group is responsible for defining product specifications, requirements and roadmap. Supporting all sales activities and efforts; Marketing materials, customer presentations and product demonstrations, supporting customer projects and technological partnerships.
Responsibilities:
Responsible for product platform life cycle: analyze and assess market requirements, product requirements, see-through development cycle with CTO & RD teams, and delivery to the end customer.
Strategic planning and creation of product roadmaps, based on methodological market analysis and creativity
Responsible for product specifications (MRD, PRD). Leading product activities with RD, and new product development with the CTO team.
Analysis of customer requirements, specifications, and architectures to identify potential opportunities and market needs
Create and deliver product collaterals including product presentations, datasheets, and case studies
Supporting customer product evaluation process from product presentation, technical discussion, POCs, and commercial phases
Act as a focal-point while working closely with all areas of the company as Research, Development, Project Management, Marketing, Business Development, and Sales

we are looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
What you'll be doing:
Physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.
Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems.
Daily work involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
Taking part inflows development.

We are now looking for a Principal Formal Verification Engineer to join our our company Networking team!
As a Principal Formal Verification Engineer in our companys Networking Business Unit, you will play a critical role in shaping the formal strategy and execution of complex, high-performance silicon designs that power data centers, AI infrastructure, networking, and storage systems. This is a senior technical leadership role, requiring deep hands-on experience and a strong execution mindset.
You will join a passionate and expert team responsible for applying formal methods to validate designs at the highest level of rigor. This role offers the opportunity to work at the cutting edge of formal verification, influence architecture, and collaborate across functions to drive best-in-class silicon quality.
What Youll Be Doing:
Define and execute advanced formal verification strategies for complex digital blocks and systems.
Lead formal activities across multiple projects, ensuring scalability, completeness, and convergence .
Guide the development of formal testbenches, properties, assertions, and coverage models.
Collaborate with architects, RTL designers, and DV teams to identify formal targets and maximize design verification efficiency.
Provide technical leadership and mentoring to other formal engineers and contribute to the growth of formal expertise within the organization.
Evaluate and deploy state-of-the-art formal tools, flows, and methodologies to continuously improve formal verification coverage and impact.

We are now looking for a Formal Verification Manager to join our company Networking team!
As a Formal Verification Manager in our companys Networking Business Unit, you will lead a team of highly skilled formal engineers responsible for verifying the next generation of our companys cutting-edge Network products and GPU technologies.
This is a unique opportunity to make a real impact at the heart of our companys AI and HPC revolution, while working in a fast-paced, innovative environment.
You will be part of a passionate and experienced team using leading formal verification tools and methodologies to ensure design correctness at the highest level. Your work will influence key architectural decisions and help deliver world-class silicon solutions for data centers, high-performance computing, networking, and storage applications.
What Youll Be Doing:
Lead and grow a team of formal verification engineers focused on pre-silicon Formal verification of complex digital designs.
Define and drive formal verification strategies and methodologies to prove the correctness of designs across multiple projects.
Collaborate closely with Architecture, Design, DV teams to identify verification needs and drive closure.
Provide technical guidance, mentoring, and support to engineers in the team.
Own the planning and execution of formal verification deliverables to ensure high quality and timely tapeouts.

We are now looking for a Senior Chip Design RTL Design Engineer for the Switch Silicon group.
As a Chip Design Engineer at our company's Networking business unit, you'll join a group of passionate engineers to design and implement the next generation state of the art Switch Silicon chips. In this position, you'll make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!
What you'll be doing:
Work in a combined design and verification team which develops some of the switch silicon core units.
Plan and Design RTL units / blocks according to Arch & Micro arch specifications under challenging constraints with high orientation to power, area, and performance.
Build reference models, verify and simulate chip blocks/entities according to specifications.
Work closely with multiple teams within organizations such as Architecture, Micro- Architecture, and FW.