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We are looking to hire a Chip Design Verification Engineer to join our Chip Design group. The work environment is versatile, educational, dynamic and challenging as our employees are currently working on innovative, next-generation networking devices at the forefront of technology in terms of performance and power efficiency. Daily work involves all aspects of chip development: Design, Micro- Architecture, Firmware, and Verification. Work with the best and become one of the best!

What you will be doing:

Work in a combined design and verification team which develops core units within the Networking silicon.

Build reference models, verify and simulate chip blocks/entities according to specifications and performance requirements.

Work closely with multiple teams within organizations such as Architecture, Micro- Architecture, FW and Post-Silicon validation.

We are now looking for a Chip Design Verification Engineer. We are seeking a verification engineer to join the chip design methodologies team. The team is in charge of the verification methodologies, shared code, training, and embracing new technologies. One of our main goals is to make sure that the team works in an efficient manner, and provides high-quality deliveries. This position offers the opportunity to have real impact in a dynamic, technology-focused company.

What you'll be doing:

Develop shared verification code and solutions to be widely used by the chip design team.

Develop groundbreaking methodologies to create a flawless experience for verification engineers to keep the focus on new problems.

Collaborate with the design automation team to provide end-to-end solutions that combine verification, simulation, and automation.

Get in touch with EDA vendors to learn about cutting-edge tools/technology and apply them into our verification process.

Understand the design, define the verification scope, develop the verification infrastructure and verify the correctness of the design.

Collaborate with designers, verification specialists to accomplish your tasks.

Develop training sessions.

We are looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you'll be doing:

Physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.

Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems.

Daily work involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.

Taking part inflows development.

We are looking for best-in-class Physical Design CAD Engineer to join our outstanding Networking Silicon engineering team, developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you'll be doing:

You will be in charge of developing physical design, synthesis, STA and Logic eq methodologies for implementation of networking chips and SOCs.

Work closely with block owners. full Chip STA engineers and project managers to assure high quality and timely convergence.

Come up with unique and creative solutions to the state of the art physical design problems that are needed for Our chips.

Additional responsibilities include participating and developing flow and tool methodologies for chip floorplan, power and clock distribution, P&R, timing analysis and closure, power and noise analysis and back-end verification across multiple projects.

We are a leader in high-performance computing and machine learning, seeking a HW program manager with technical skills for HW R&D. This role involves program management of our Interconnect products, contributing to next-gen data centers.

As a top supplier of InfiniBand and Ethernet solutions, We offer best-in-class adapter cards, switches, cables, and software to optimize data center performance. We serve markets like high-performance computing, enterprise, data centers, cloud computing, big data, and Web 2.0. Our Ethernet solutions benefit industries such as Media and Entertainment with Datastream and TCP/IP acceleration. We are renowned as a desirable employer, attracting talented and forward-thinking individuals. If you're creative and autonomous, we want to hear from you!

What you'll be doing:

Build, manage, and implement comprehensive long-term programs, including setting timelines, allocating resources, and setting up progress milestones.

Work with engineers from different teams to ensure consistency with company strategy, commitments, and goals.

Facilitate teamwork and cooperation among team leaders to ensure accountability on their tasks and deadlines.

Capable of foreseeing and handling risks associated with constant change through proper prioritization. Come up with innovative solutions to difficult problems, and co-develop solutions and mitigation strategies.

We are looking for a talented Signal Processing and Communications Engineer to bridge the gap between simulation and real-world performance for high-speed wireline communication links. In this role, you will analyze lab results to refine development simulators and align them closely with actual SerDes performance, ensuring future designs are driven by real measurements, not just theoretical models. You will play a critical role in optimizing current designs for faster, more reliable chip bring-up and shaping the architecture of next-generation solutions. As part of the algorithm team, you will be actively involved in debugging unique and complex phenomena observed in the lab, working alongside post-silicon engineers to directly influence product performance. Separately, this role also provides a rare opportunity to gain broad system-level understanding, offering visibility into how the SerDes integrates and interacts within the larger chip architectureinsight typically beyond the standard algorithmic scope.

You will collaborate closely with analog and digital designers, signal integrity experts, and other cross-functional teams to ensure simulation models and lab results accurately represent real-world system behavior. If you are passionate about solving complex signal processing challenges and working at the forefront of technology, we want to hear from you.

What you will be doing:

Develop HW tools and flows to improve lab debuggability and visibility.

Correlate simulation results with lab measurements to improve model accuracy.

Work closely with cross-disciplinary teams to ensure accurate and reliable model representation.

Find performance bottlenecks

Characterize and evaluate analog and digital blocks in the lab to contribute to the DSP architecture and modeling strategies for next-generation SerDes designs.

We are seeking a highly skilled and expert Verification Lead to join our PCIe Firmware team. In this role, you will be responsible for supervising the verification plans, monitoring their execution within the teams, guiding engineers through the verification implementation, and tracking coverage, Coverity, and other relevant statistics. You will be joining a team dedicated to developing groundbreaking technology and building the core technology of next-generation devices across various fields, including low-level C layer between hardware and firmware, C++ verification environment, automation challenges, and Python testing environment.

What youll be doing:

Develop and lead verification plans, ensuring they are driven effectively within the teams.

Provide guidance to engineers on verification implementation within the verification environment.

Monitor coverage, Coverity, and other statistics to ensure comprehensive verification and optimization of next-generation NVIDIA products.

Work closely with firmware design, chip design, software, and architecture teams to define and craft both legacy and new low-level firmware flows.

Enhance methodologies and automated processes to improve efficiency and effectiveness.

We are looking for a Chip-Design Verification Engineer to join our Switch Silicon team. As a Chip Design Verification Engineer at NVIDIA's Networking business unit, you'll join a group of passionate engineers to design and implement the next generation state-of-the-art Switch Silicon chips. In this position, you'll make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!

What you'll be doing:

Work in a design and verification team that develops the front-end design for the Switch silicon and the GPU.

Develop verification components and reference models, as well as verify and simulate chip blocks according to specifications under challenging constraints with a high orientation to power, area, and performance.

Work closely with multiple teams within organizations such as Architecture, Micro- Architecture and FW.

We are seeking a highly motivated High-Performance System Architect to join our team of experts and help shape the future of high-performance and ML / AI computing. Our next-generation Infiniband and NVL systems will be at the forefront of connecting and powering the world's most advanced compute clusters, from supercomputers used in AI research to high-performance clusters used at almost every industry today, such as car and Pharmaceutical. As a high-performance system architect, you will have the opportunity to work on some of the most cutting-edge technology and help to drive the innovation of our next generation networks that will be used by top researchers and engineers around the world.

What youll be doing:

Define the Infiniband and NVL system architecture end-to-end, by internal requirements and customers requirements through all product life cycles (post/pre silicon, on deployments).

research of various solutions to enable the next large-scale-high-performance computing clusters. The position spans over various layers from algorithms, software, firmware, and HW.

The architect should have experience in developing models for simulations, analyzing simulation results and development of optimization algorithms.

Collaborate with cross-functional teams, including other architecture teams, logic design, system software, firmware, and research teams, to ensure the successful execution of the project.

We are looking for a ASIC SOC Design Engineer.
Responsibilities:
Be a significant part of the SoC Silicon team, developing next generation IOT and AI chips.
Take part in all aspects of digital design from architecture and specification, RTL design and verification.
Close collaboration with the Physical Design team, and supporting SW and Production teams.
Contribute to the development of a very complex state-of-the-art technological project.
Integration of sophisticated sub-systems.

We are seeking a highly motivated High-Performance System Architect to join our team of experts and help shape the future of high-performance and ML / AI computing. Our next-generation Infiniband and NVL systems will be at the forefront of connecting and powering the world's most advanced compute clusters, from supercomputers used in AI research to high-performance clusters used at almost every industry today, such as car and Pharmaceutical. As a high-performance system architect, you will have the opportunity to work on some of the most cutting-edge technology and help to drive the innovation of our next generation networks that will be used by top researchers and engineers around the world.

What youll be doing:

Define the Infiniband and NVL system architecture end-to-end, by internal requirements and customers requirements through all product life cycles (post/pre silicon, on deployments).

research of various solutions to enable the next large-scale-high-performance computing clusters. The position spans over various layers from algorithms, software, firmware, and HW.

The architect should have experience in developing models for simulations, analyzing simulation results and development of optimization algorithms.

Collaborate with cross-functional teams, including other architecture teams, logic design, system software, firmware, and research teams, to ensure the successful execution of the project.

We are looking for a Experienced SW Embedded engineer.
Responsibilities:
Engage with customers, architecture, and product teams to define the right features and solutions to our product portfolio.
Design and implement features optimized for our flagship IoT products, specializing in low-memory and low-power consumption.
Drive end-to-end development of features, ensuring performance, power consumption, reliability, and maintainability.
Collaborate closely with cross-functional teams, including Software, System Validation, Architecture, and Product, to deliver high-quality solutions.

We are seeking a Senior Deep Learning Researcher for an excellent opportunity! This role provides an outstanding opportunity to engage in groundbreaking innovation and contribute to advancing diffusion-based technologies. You will work with pioneering methodologies and tools, crafting solutions that push the boundaries of AI capabilities.

What you'll be doing:

Invent and build ground-breaking techniques for efficient multi-modality model creation and publish the findings in leading journals and conferences.

Combine traditional diffusion technologies with the latest and greatest LLMs.

Contribute to our AI enterprise software to ensure robust and scalable solutions.

Collaborate with internal and external teams worldwide to drive research and development in multi-modal learning, using different professions and resources across the company.

Partner with leading scientific organizations and industry pioneers to remain at the forefront of technological advancements and integrate the latest innovations into practical applications.

Our Networking Clock design team is looking for experienced top notch ASIC design engineer to work on next generation of our Networking chips. We're looking for profound and multi-disciplinary background in Clock design domains to lead Clocks Micro-Architecture activities. This role requires working with multiple teams as Architecture, IP, Physical design, Timing and Post-Si teams. Complexity of clocking scheme has grown substantially over recent chip generations with increased focus on performance, power and quality. Modern Clocking design needs to balance high frequency clocks with power, DFx, noise, circuit and physical design constraints.

What you will be doing:
Working on next generation of Networking Switch, NIC and SoC products.
Micro architect and design next generation clock topologies and modules.
ASIC Clock scheme definition.
Improve Power, Performance, and Area (PPA) of state-of-the-art chips by evaluating trade-offs across DFx, Physical Implementation, Power Optimization and Ease of timing closure to innovate and implement new Clocking topologies in RTL.
Collaborate with Physical design and timing team to evaluate Clocking concerns and come up with solutions for supporting high speed Clocking.
Understand physical aspects of the chip and develop enhanced clock distribution techniques.
Get involved in end-to-end cycle of ASIC execution starting from micro-arch, design implementation, design fixes, sign-off checks and all the way to Silicon bringup.
Support Post-Si debug, characterization and productization activities.

We are looking for best-in-class Chip Design Engineer to join our outstanding Networking Silicon engineering team. We are developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! Come and take a significant part in designing and verifying our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a huge impact in a technology-focused company.

What you will be doing:
Join accelerators IP group in Beer-Sheva/ Tel-Aviv, working on RiscV platform unit and cache coherence IP.
design for chip blocks according to specifications under challenging constraints and with high orientation to power, area and performance.
Daily work might involve any or all aspects of chip development: uarch , Design.
Work closely with Firmware and other groups around the globe.