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Required Tetragon Software Engineering Technical Leader
Job Description
Meet the Team
We are the company founded by the creators of Cilium and eBPF. Isovalent builds open-source software and enterprise solutions solving networking, security, and observability needs for modern cloud native infrastructure. The flagship technologies, Cilium and Tetragon, are the choice of numerous, industry-leading, global organizations.
We believe in fostering an inclusive workplace where every team member feels valued, respected, and empowered. We believe that every employee contributes to our success, and we are committed to fostering an environment where everyone can thrive. We encourage candidates from all backgrounds to apply and join us in our mission to deliver exceptional products and services.
Your Impact
Tetragon is a flexible, Kubernetes-aware observability and security tool that delivers real-time insights and enforcement. Leveraging the power of eBPF, Tetragon provides low-overhead, in-kernel visibility and intelligence across diverse environments.
As a Technical Leader, you will be at the forefront of advancing Tetragons capabilities. You will guide architectural direction while staying deeply engaged in building the systems that power our platform. Your impact will span designing high-performance data pipelines, optimizing database and distributed system performance, and ensuring massive streams of system events can be ingested, aggregated, and distilled into meaningful intelligence.
You will collaborate closely with teams across, including Hypershield and Splunk, to create the integration points that transform raw data into actionable insights for enterprise security. In this role, youll solve some of the most complex system-level challenges in observability and infrastructure, helping Tetragon evolve to meet the needs of modern cloud-native environments.
What youll do:
Develop high-quality Go (and eBPF) code for the Tetragon project.
Design and implement new Tetragon features to enhance its capabilities for Runtime security detection and enforcement
Design and optimize systems for large-scale Tetragon deployment and operation in K8s or VM platforms
Architect infrastructure that converts raw event data into intelligence streams with minimal performance overhead.
Contribute to open-source projects and represent Isovalent in community discussions.
Participate in architecture reviews, code reviews, and documentation.

We are seeking PHY Algorithm Technical Leader, Silicon One Israel
Meet the Team
You will join the SerDes System Algorithm team within Silicon One High Speed in Israel, part of our silicon development organization. The team works across modem technology, system modeling, and signal processing for high-speed SerDes devices.
Silicon One is at the center of our ASIC group, building next-generation network devices for AI networks, the 5G era, and the future of routing. Our design center brings silicon hardware and software disciplines together in one site, combining a small-team startup atmosphere with the scale and stability.
Your Impact
As a PHY Algorithm Technical Leader, you will provide technical leadership for the development, modeling, configuration, and optimization of algorithms for advanced SerDes modem systems. You will work with the latest silicon technologies and processes to help build large-scale, complex devices at the edge of feasibility.
Your work will contribute to Silicon One, a unified and programmable silicon architecture designed for service provider and web-scale markets. The role requires technical depth in digital signal processing, modem behavior, and using MATLAB for algorithm development, with the ability to guide algorithm work from initial concept through advanced SerDes system implementation.
Provide technical leadership for research, design, and development of PHY and modem algorithms for high-speed SerDes devices.
Define and use system models to analyze modem behavior, signal-processing performance, architecture constraints, and algorithm tradeoffs.
Guide modem configuration, tuning, and optimization to improve performance, robustness, and implementation feasibility.
Use MATLAB for algorithm development, simulation, testing, and data analysis.
Guide technical decisions, review algorithm tradeoffs, and mentor engineers on complex PHY and modem development tasks.
Lead cross-functional technical collaboration with system, silicon hardware, and software teams to move algorithms from modeling into practical implementation.
Support lab-based validation and debug activities when required.

Required IC Package Layout Designer
Job Description
Meet the Team
Join the Package Design Team at Silicon One in Israel, a group leading the way in developing our groundbreaking silicon solutions for next-generation networking. As a collaborative team at the center of our silicon development, we design and optimize advanced package solutions for some of the industrys most sophisticated ASICs. Youll work directly with experts in layout, signal integrity, and power distribution, shaping innovative methodologies and driving the evolution of high-performance networking technologies.
Your Impact
This role offers a unique opportunity to make a significant impact on the future of networking innovation within the Silicon One initiative. As a layout engineer, you will drive the entire package design layout process-from planning and optimization to execution-ensuring the delivery of high-speed, robust, and scalable solutions for global networks. You will work closely with engineers, define strategies, and collaborate across multi-functional teams to accelerate the creation of industry-leading packages. Youll join a passionate community dedicated to changing how the world connects, works, and learns, while building strong partnerships and fostering collective success.
Responsibilities:
Lead package layout design while planning and driving schedules from initial concept through full implementation.
Optimize package pinouts, stack-ups, power distribution, and high-speed routing, balancing performance and manufacturability
Collaborate with signal integrity (SI) and power integrity (PI) teams to ensure design quality and efficiency
Enhance design methodologies and partner with vendors to improve product quality and efficiency
Drive innovation in package solutions for our next-generation ASICs.

We are excited to announce that the Silicon One team is undergoing rapid growth, and we are looking for a Senior C++ Software Developer.
Meet the Team
Join the Silicon One team developing a unified silicon architecture for web-scale and service provider networks. Our silicon team provides an outstanding, unique experience for ASIC and Software engineers by combining the resources offered by a sizable multi-geography silicon organization with the startup culture and breadth of growth opportunities that working in a smaller team can provide.
Your Impact
Craft and develop software driving the world's most complex infrastructures
Gain intimate knowledge of world-class silicon and programming models
Work with architecture and design teams to define the next generation of ASIC products being developed.

We are seeking a Physical Design Technical Leader.
Meet the Team
Physical Design team within Silicon One is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.
We demonstrate the latest silicon technologies and processes to build the largest-scale and most complex devices, pushing the boundaries of feasibility.
Your Impact
You'll be part of the Silicon One team, which is at the heart of our software and ASIC design efforts.
You'll handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.

Required PHY Firmware Technical Leader
Meet the Team
Join the Silicon One PHY System team, part of our core silicon development group.
Our team is responsible for PHY and system-level aspects of some of the most advanced networking devices in the industry, including PHY firmware, calibrations, system definitions, operations, and post-silicon validation.
We work with the latest silicon technologies and processes to build large-scale, highly complex devices at the edge of feasibility. Youll be part of a unique design center that hosts all silicon HW and SW disciplines under one roof, operating in a startup-like environment within a stable, world-leading company.
We are transforming the industry with a unified, programmable silicon architecture that powers our future routing portfolio and helps shape the Internet for decades to come.
Your Impact:
Develop PHY firmware and system-level features for advanced networking ASICs
Participate in post-silicon validation, including lab bring-up, debugging, and performance analysis
Collaborate closely with PHY, system, firmware, and silicon design teams
Contribute to defining system operation modes and end-to-end device behavior
Help drive the development of next-generation, high-scale networking solutions using cutting-edge silicon technologies
Who Youll Work With:
The Silicon One group, the center of our ASIC design efforts
Cross-functional teams including silicon design, firmware, and system
Global teams working together to deliver game-changing networking devices

Required Software Modeling Team Leader
Job Description
Meet the Team
Join the Silicon One team in developing a unified silicon architecture for web-scale, service provider, and enterprise networks. Our silicon team provides an outstanding, unique experience for Software and ASIC engineers by combining the resources offered by a sizable multi-geography silicon organization and a large campus with the startup culture and breadth of growth opportunities that working in a smaller ASIC team can provide.
Your Impact
As the leader of the team, you will be responsible for delivering a state-of-the-art functional simulator for the SiliconOne family of routing and switching devices. This simulator is a critical product that streamlines the development process and significantly reduces time-to-market.
In this role, you will:
Lead and mentor and scale the team to 7-10 engineers, fostering a collaborative and inclusive environment
Oversee the design and delivery of a high-performance, reliable, and user-friendly behavioral model for SiliconOne devices
Collaborate closely with cross-functional teams including ASIC Architecture, Software, and Hardware to align goals and ensure seamless execution
Champion engineering excellence by modeling hands-on problem solving and debugging best practices
Guide team members in their professional development with tailored growth plans and regular feedback.

Required ASIC Design Engineer - Silicon One
Job Description
Meet the Team
Join the Silicon One Front-End Design team, at the core of our silicon development. Our engineers cover the full spectrum of chip design: definition, architecture, micro-architecture, RTL design, verification, signoff, and validation.
We leverage cutting-edge silicon technologies and methodologies to develop the largest-scale and most advanced devices, pushing the boundaries of whats possible.
We are transforming the industry with a unified, programmable architecture powering our future routing portfolio and shaping the Internet for decades to come.
Your Impact
Write and review micro-architecture specifications
Implement RTL (Verilog/SystemVerilog) to meet timing, performance, and power requirements
Contribute to full chip integration, timing methodology, and analysis
Collaborate with verification engineers to resolve bugs and achieve coverage closure
Work with the physical design team to close timing and PnR issues
Support design methodology evolution and best practices
Perform debug, root-cause analysis, and post-silicon validation in the lab.

Silicon One is seeking a Physical Design Group Leader.
Meet the Team
Physical Design team within Silicon One is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.
We demonstrate the latest silicon technologies and processes to build the largest-scale and most complex devices, pushing the boundaries of feasibility.
Your Impact
You'll be part of the Silicon One team, which is at the heart of our software and ASIC design efforts.
As the Physical Design Group Leader, you will provide strategic and technical leadership to a team of engineers, guiding them through the entire chip design lifecycle. You will be responsible for the group's output, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.

Silicon One is seeking a CAD Engineer to join the Silicon One Physical Design team.
Meet the Team
You'll be part of the Silicon One team, which is at the heart of our software and ASIC design efforts.
As part of our team, youll contribute to the development of our next-generation network devices-Silicon One. Our team operates in a startup-like environment within a stable and leading corporation.
Our design center is uniquely equipped, hosting all silicon hardware and software development fields under one roof.
We are revolutionizing the industry by building a new internet for the 5G era, providing a unified, programmable silicon architecture that serves as the foundation for all of our future routing products. Our devices are designed to be universally adaptable across service providers and web-scale markets, catering to both fixed and modular platforms. They deliver high speed without compromising on programmability, buffering, power efficiency, scale, or feature flexibility.
Silicon One is a ground-breaking, groundbreaking technology that will serve our customers and end users for decades to come. The Internet now has a new, faster, better, and safer engine!
Your Impact
You'll be joining our Physical Design team within Silicon One, which is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.
Our Backend Engineers handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.
You will be leveraging your backend and physical design experience to drive the development, optimization, and innovation of CAD methodologies and tools, ensuring the highest quality and efficiency in our chip design flows from RTL to GDS.

We are seeking an accomplished Senior Software Engineer with expertise in architecture and delivery, CI, operations and most importantly AI assistance. We invite you to apply and contribute to our mission of advancing networking and security within Kubernetes environments.
Architect and Develop AI assisted tooling to support and improve developer experience
Collaborate in code reviews, architectural discussions, customer support escalations, and contribute to comprehensive technical documentation.
Implement CI/CD pipelines to streamline operations.

Silicon One is seeking a CAD Engineer to join the Silicon One Physical Design team.
Meet the Team:
You'll be part of the Silicon One team, which is at the heart of our software and ASIC design efforts.
As part of our team, youll contribute to the development of our next-generation network devices-Silicon One. Our team operates in a startup-like environment within a stable and leading corporation.
Our design center is uniquely equipped, hosting all silicon hardware and software development fields under one roof.
We are revolutionizing the industry by building a new internet for the 5G era, providing a unified, programmable silicon architecture that serves as the foundation for all of our future routing products. Our devices are designed to be universally adaptable across service providers and web-scale markets, catering to both fixed and modular platforms. They deliver high speed without compromising on programmability, buffering, power efficiency, scale, or feature flexibility.
Silicon One is a ground-breaking, groundbreaking technology that will serve our customers and end users for decades to come. The Internet now has a new, faster, better, and safer engine!
Your Impact:
You'll be joining our Physical Design team within Silicon One, which is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.
Our Backend Engineers handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.
You will be the tech lead for CAD within the team, leveraging your extensive backend and physical design experience to drive the development, optimization, and innovation of CAD methodologies and tools, ensuring the highest quality and efficiency in our chip design flows from RTL to GDS.
We demonstrate the latest silicon technologies and processes to build the largest-scale and most complex devices, pushing the boundaries of feasibility.

Required Leader, Software Engineering
Job Description
Meet the Team
The AI Software & Platform Group incubates and delivers Generative AI based solutions to reinvent our existing Products and how customers interact with them. Our Group is also introducing new offerings that help customers roll out Generative AI at scale while doing so responsibly. Ultimately we are doing so through internal platforms that unlock the benefits of this technology for our teams and partners across our Security, Enterprise Networking, Collaboration and Splunk portfolios.
Your Impact
As an Engineering Manager in Cloud Control, youll play a key role in
building the next-gen platform that brings together our product portfolio under one AI-native roof. Youll lead a growing engineering team in our TLV WeWork office (dedicated space with all the perks) while collaborating with global company groups on cross-product AI solutions. Own the design and implementation of functional and non-functional UI features.
Partner with your team to plan epics, deliverables, and sprints.
Work with org architects to drive functional and non-functional product enhancements.
Collaborate with other groups to deliver AI-native, cross-product integrations.
Actively contribute to the codebase, review PRs, and ensure engineering excellence.
Build and mentor a high-performing team while navigating the challenges of a large enterprise with a startup mindset.

Required Tetragon Threat Detection Engineer - Isovalent
About this role:
Cilium Tetragon is a flexible, Kubernetes-aware security tool, with real-time observability and enforcement. Leveraging the power of eBPF, Tetragon offers a low-overhead, in kernel solution that enhances security posture by monitoring system behaviors such as process executions, system call activities, and both network and file access events.
Tetragon Threat Detection Engineers primarily focus on creating and maintaining
Tetragon runtime security policies, based on the latest threat intelligence, vulnerability disclosures, and their own research.
Policies can act either as a mitigation to known vulnerabilities or as monitoring and protection against unknown security issues.
What youll do:
Develop and maintain Tetragon runtime security policies to ensure customers have good visibility of suspicious activity on their infrastructure and are protected against the latest emerging threats
Help design frameworks and architectures that allow customers to easily consume policies and understand their overall security posture
Monitor vulnerability disclosures (CVEs) and the latest threat intelligence to develop Tetragon runtime security policies
Work with software engineers at Isovalent and us to improve and enhance the capabilities of Tetragon security policies
Interact with solution architects and customers as necessary to support and deploy Tetragon security policies in production
Publish content and give talks based on your work.

We are seeking an experienced and highly motivated C++ Software Engineer to join the Compiler team of our Network Technology R&D organization, contributing directly to the evolution of next-generation networking products.
Meet the Team:
Our team builds firmware, SDKs, simulators, and compilers for the Silicon One architecture - the industrys first routing and switching silicon architecture unifying networking across all layers. You will work on pioneering technology that powers the future of the Internet.
You will be part of a global team working on the newest generation, which will be integrated across the entire portfolio of our devices.
You will collaborate with worldwide distributed R&D centers, gaining exposure to some of the most talented engineers in the networking industry. We look for people who love technology and engineering-people who thrive on innovation, continuous learning, and challenging whats possible.
Your Impact
Design, implement, and test a state-of-the-art optimizing compiler for Silicon One
Evaluate and optimize code performance, including debugging, code generation improvements, and pipeline analysis
Develop, optimize, and enhance the compiler backend to fully leverage cutting-edge hardware capabilities
Solve complex resource management challenges across hardware pipelines
Design and implement new P4 language features that empower network application developers
Build and maintain the compiler toolchain for custom networking applications
Contribute to libraries, analysis tools, and supporting infrastructure
Collaborate with cross-functional hardware and software teams
Work closely with ASIC engineers on next-generation IC design, influencing hardware through compiler insights prior to tape-out.