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we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Physical Design Engineer specializing in SoC EMIR to join our local engineering powerhouse from the ground up.
This is a unique opportunity to take on meaningful technical ownership in a new site, executing the backend power methodologies for chips that power the world's largest AI clusters. As an EMIR Engineer, you will be a core technical contributor ensuring the power robustness and long-term reliability of our high-performance connectivity silicon.
You will be responsible for SoC EMIR Analysis to ensure our products meet aggressive voltage drop and reliability targets in advanced FinFET process nodes, directly impacting the performance and yield of chips operating in the worlds most demanding AI and cloud environments.
Key Responsibilities
Take responsibility on IR drop analysis and signal/power electromigration (EM) of very complex chip
Collaborate closely with Physical Design team to insure a full power integrity
Partner with Package Design engineers to perform Chip-Package co-analysis (CPM)
Understand root-cause analysis for voltage drop violations and EM risks.

we are looking for a Wafer-Scale System: Computation (LLM) and Communication (NoC) Co-Design.
Responsibilities:
Conduct cutting-edge research on the co-design of communication and computation for wafer-scale systems. On the communication side, the work focuses on architecting Networks-on-Chip, providing scalable, high-bandwidth, and ultra-low-latency interconnects that efficiently span multiple dies and support fine-grained data movement. On the computation side, the research emphasizes optimizing and mapping training and inference workloads to fully exploit wafer-scale resources, improving performance, scalability, and energy efficiency through intelligent task placement and scheduling.
Investigate various aspects of system design, including:
Network-on-Chip design, further including Topology exploration, routing algorithms, and protocol/flow-control design to support high-throughput collective communication, low-latency synchronization, and efficient model/data parallelism
Expressing and Mapping LLM Parallelism to Wafer-Scale System that simplify LLM parallelism (e.g., tensor, pipeline, and data parallelism) and efficiently map training and inference workloads onto wafer-scale system

We are seeking an experienced Staff/ Principal Architect to lead the architecture of high-performance connectivity solutions, with a strong focus on PCIe, high-speed networking, and Ethernet-based systems.
This role will define next-generation architectures for AI infrastructure, working at the intersection of silicon, system, and protocol design. You will play a key role in shaping innovative solutions that enable hyperscale customers to build scalable, high-bandwidth, and low-latency systems.
This is a unique opportunity to join a new and growing Israel site, influence technical direction, and take ownership of critical architectural decisions impacting industry-leading products.
Key Responsibilities
Define and drive system and chip-level architecture for high-speed connectivity products
Lead architecture for PCIe-based interconnects, networking protocols, and Ethernet subsystems
Analyze system requirements and translate them into scalable and efficient hardware architectures
Drive tradeoff analysis across performance, power, latency, area, and cost
Collaborate with cross-functional teams including RTL, Physical Design, Firmware, Validation, and Product Engineering
Define and review micro-architecture specifications and ensure alignment across teams
Contribute to standard-based and custom protocols for next-generation AI infrastructure
Support performance modeling, simulation, and architectural validation
Work closely with customers and partners to understand emerging use cases and requirements
Mentor engineers and help build strong technical leadership within the Israel R&D center.

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a talented Staff/ Principal Design Verification Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful ownership in a new site, developing the verification environments that ensure our next-generation AI silicon performs flawlessly.
As a Staff/ Principal Design Verification Engineer, you will be a vital contributor to the quality and reliability of our Israel R&D center. You will work on the front lines of functional verification, developing testbenches and environments that validate high-performance digital blocks, subsystems, and full-chip designs. You will tackle complex verification challenges that ensure our connectivity solutions meet the rigorous demands of the world's largest AI clusters. If you thrive on solving technical puzzles and want to play a key role in delivering cutting-edge AI infrastructure connectivity, this is your opportunity.
Key Responsibilities
Verification Environment Development
Contribute to the design and development of ASIC verification environments, focusing on unit-level and subsystem functional blocks
Develop and maintain SystemVerilog/UVM-based components including traffic generators, monitors, and checkers to ensure robust testing
Execute detailed verification plans for challenging digital designs, ensuring all functional requirements are met and verified
Coverage & Quality Assurance
Implement functional coverage models and analyze results to identify gaps in the verification process
Drive designs toward 100% verification closure through comprehensive test development
Contribute to verification methodology improvements and best practices
Debug & Cross-Functional Collaboration
Work closely with design engineers to identify, root-cause, and resolve complex hardware bugs early in the development cycle
Apply analytical skills and debugging techniques to solve intricate verification challenges
Collaborate effectively in a fast-paced, team-oriented R&D environment.

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, We are looking for a Physical Design CAD Engineer with at least 3 years of hands-on experience in digital implementation flows. The ideal candidate is highly technical, curious, and eager to drive innovation by combining strong physical design knowledge with modern automation and GenAI-based methodologies.
This is a unique opportunity to take on meaningful technical ownership in a new site, implementing the parasitic extraction (PEX) methodologies and flows for chips that power the world's largest AI clusters. As a foundational member of the team, you will be responsible for the accuracy and efficiency of our extraction environment, ensuring that our high-speed designs are modeled with the highest precision from RTL to GDSII.
Key Responsibilities
The Engineer will develop, maintain, and improve CAD flows and methodologies for physical design teams, supporting advanced implementation stages from synthesis through place and route, timing closure, power optimization, and signoff readiness.
Key responsibilities include:
Develop and support physical design CAD flows using industry-standard EDA tools
Build automation infrastructure for implementation, analysis, reporting, and debug
Support design teams in areas such as synthesis, floorplanning, placement, CTS, routing, timing, power, and physical verification
Create scripts and utilities to improve productivity, quality of results, and flow robustness
Support and enhance flows based on Synopsys Fusion Compiler
Explore and integrate GenAI solutions to accelerate debug, automate repetitive tasks, improve reporting, and enhance engineering productivity
Analyze tool results, logs, QoR metrics, timing reports, congestion, utilization, power, and design-rule issues.

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Physical Design Engineer specializing in SoC EMIR to join our local engineering powerhouse from the ground up.
This is a unique opportunity to take on meaningful technical ownership in a new site, executing the backend power methodologies for chips that power the world's largest AI clusters. As an EMIR Engineer, you will be a core technical contributor ensuring the power robustness and long-term reliability of our high-performance connectivity silicon.
You will be responsible for SoC EMIR Analysis to ensure our products meet aggressive voltage drop and reliability targets in advanced FinFET process nodes, directly impacting the performance and yield of chips operating in the worlds most demanding AI and cloud environments.
Key Responsibilities
Take responsibility on IR drop analysis and signal/power electromigration (EM) of very complex chip
Collaborate closely with Physical Design team to insure a full power integrity
Be responsible on IR architecture for timing convergence
Partner with Package Design engineers to perform Chip-Package co-analysis (CPM)
Understand root-cause analysis for voltage drop violations and EM risks
Be responsible and go-to person for any IR related issues.

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Silicon Technical Program Manager to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, leading the physical implementation strategy for chips that power the world's largest AI clusters.
As an Technical Program Manager, you will be the key architect of our silicons operational reality. You wont just track timelines - you will help establish our local execution culture and technical standards, owning the cross-functional journey of transforming complex logic into high-performance silicon.
Key Responsibilities
Drive and manage ASIC development and subsystems from concept through to production in collaboration with internal teams and external vendors.
Provide hands-on program management throughout the full development cycle of silicon and firmware, including concept, design, development, fabrication, validation, and production release.
Work closely with the software, hardware, and architecture teams to align with product requirements and ensure all constraints are met.
Lead process improvements across multiple teams and functions to drive better collaboration and efficiency.
Independently manage complex projects with minimal supervision, ensuring timelines and milestones are met.
Deliver high-quality ASIC solutions products while collaborating with product management and architecture teams.

we are seeking a skilled and motivated Data Scientist. This individual will play a pivotal role in identifying key data points for collection, developing strategies to accumulate data and deriving actionable insights an anomaly based on a solid foundation of relevant know-how. Also, will also be responsible for creating, testing, and deploying scripts and methods for data collection and analysis to support decision-making. The Engineer will collaborate with cross-functional teams to identify critical data sources to determine the most effective data collection strategies, will develop automated and scalable data collection pipelines, will ensure data quality, integrity, and consistency across all sources and may use AI techniques to refine the results toward failures predictions.

This is an excellent opportunity to work on challenging and complex projects at advanced technology environment with major companies in the semiconductor domain!

This role will enable you to improve your technical skills, working with the industry leading engineers over a wide range of topics while interacting with the business world.

The Application Engineer will provide expert level technical customer Pre-Sale and post-sale support for Cadence customers in Physical Design area.

We are looking for a Senior AI Modeling Architect to define and model the architecture of our next-generation AI processors. In this role, you will serve as a key technical authority - bringing not only strong modeling capabilities, but also the architectural vision to propose and drive end-to-end solutions to complex design challenges.
You will work at high levels of abstraction, partnering closely with HW and SW architects to co-invent optimal solutions, validate them through simulation, and influence design decisions based on experimental data.
Responsibilities:
Model CPU/AI processor functionality and performance using SystemC and pre-silicon simulation environments
Define and drive architectural solutions - not only identify problems, but come with concrete proposals and alternatives
Partner with lead HW and SW architects to co-design features and evaluate trade-offs across the stack
Analyze bottlenecks and performance on workloads reflecting future AI use cases
Provide proof-of-concept implementations for new architectural features and design alternatives
Potentially lead feature definition in addition to the modeling role

we are looking for a Compilation Technology Expert.
This team will operate under a unique manner, as described below -
The environment
- Startup-like intensity
Small team
High ownership
High visibility
Merit is the essence, not titles
- Fast pace
Todays state of the art is tomorrows baseline
We aim to go beyond
- Incubator mindset
Take on hard challenges, dismantle, and regroup as novelty
- Elite technical culture
Strong experts
Strong standards
Strong execution.
Ratio beats seniority, not the other way around
- No artificial boundaries
We challenge assumptions, and question constraints, and leave no quarter
- Direct exposure to the latest and greatest AI technology
Real hardware
Real toolchains
Real large-scale AI applications
All pass through and impacted by our work
- First-principles thinking
out-of-the-box is a compromise
Do not accept that a box had to exist in the first place.

We are seeking an experienced C++ Developer with a strong background in building sophisticated systems to join our innovation group. This role focuses on developing a Browser Detection and Response (BDR) System aimed at enhancing browser security for users worldwide.
Key Responsibilities:
Design, develop, and maintain new complex C++ features with an emphasis on chromium browser security and internals.
Collaborate with teams across the world for productization
Contribute to the innovation and enhancement of security features within browser technologies.
Why Join Us:
Work on projects impacting billions of users.
Collaborative and innovative environment.
Competitive salary and benefits.

we are looking for a HW Architect team leader.
As HW Architect Team Leader, you will combine deep technical leadership with people leadership. You will shape next-generation networking silicon while building and mentoring a strong architecture team.
What Youll Be Doing:
Lead, manage, and mentor a team of HW architects, fostering technical excellence and innovation.
Drive research, evaluation, and architectural definition of next-generation SoCs - from product requirements through production.
Define next-generation Packet Processor / Datapath / Congestion Management architectures for high-performance, complex SoC Ethernet and NIC switches.
Lead system architecture and detailed micro-architecture definition across major functional blocks.
Collaborate cross-functionally with design, verification, modeling, software, and other architecture teams to ensure end-to-end system alignment.
Identify and evaluate new technologies, methodologies, and architectural approaches for future products.
Provide technical direction, make key architectural trade-offs, and ensure execution excellence

we are looking for a Senior HW architect.
What will you be doing?
Lead research, evaluation, and architectural definition of next-generation chips - from requirements through production.
Define next-generation Packet Processor / Datapath / Congestion Management architectures for high-performance, complex SoC Ethernet Switches.
Design the system architecture and detailed micro-architecture definition across major functional blocks.
Collaborate closely with design, verification, and modeling teams to ensure architectural intent is fully realized.
Work cross-functionally with other architecture teams to shape cohesive system solutions.
Explore and evaluate new technologies and innovative approaches for future products.

Research and Innovation Center, is looking for an experienced software engineer with expertise in Linux kernel and virtualization design + development to join our Future-Computing-Infrastructure expert group. The group designs and develops technologies for the next-generation data center aimed at accelerating AI workloads for a unique HW, optimizing compute resource utilization and reducing data-center costs. Our projects involve hardware and software architecture co-design. They require high-level system understanding, creativity and innovative thinking.
If you want to be part of something bigger, if you are a team player with excellent communication skills and motivation to revolutionize data-center technology, youre welcome on board!
What will you be doing?
Design and develop Linux kernel code related to virtual memory management and memory-tiering
Research, design and innovate methods, algorithms and supporting data-structures for managing memory hierarchies in virtualization environments
Participate in research to analyze AI-based applications performance, identify bottlenecks and optimize various decision-making mechanisms based on benchmarking results
Collaborate with professional team members and various global teams around the world on a daily basis
Challenged to think outside of the box and come up with creative ideas to deal with complex challenges within Linux kernel