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Your Impact:
Write and review micro-architecture specifications.
Implement RTL (Verilog/SystemVerilog) to meet timing, performance, and power requirements.
Contribute to full chip integration, timing methodology, and analysis.
Collaborate with verification engineers to resolve bugs and achieve coverage closure.
Work with the physical design team to close timing and PnR issues.
Support design methodology evolution and best practices.
Perform debug, root-cause analysis, and post-silicon validation in the lab.

Join the PHY System team, part of our core silicon development group.
Our team is responsible for PHY and system-level aspects of some of the most advanced networking devices in the industry, including PHY firmware, calibrations, system definitions, operations, and post-silicon validation.

We work with the latest silicon technologies and processes to build large-scale, highly complex devices at the edge of feasibility. Youll be part of a unique design center that hosts all silicon HW and SW disciplines under one roof, operating in a startup-like environment within a stable, world-leading company.

We are transforming the industry with a unified, programmable silicon architecture that powers our future routing portfolio and helps shape the Internet for decades to come.

Your Impact:

Develop PHY firmware and system-level features for advanced networking ASICs.

Design and implement PHY calibrations and system definitions.

Participate in post-silicon validation, including lab bring-up, debugging, and performance analysis.

Collaborate closely with PHY, system, firmware, and silicon design teams.

Contribute to defining system operation modes and end-to-end device behavior.

Help drive the development of next-generation, high-scale networking solutions using cutting-edge silicon technologies.

What You'll Do:

You'll develop Core Software technologies at the heart of tomorrow's leading infrastructure solutions, tackling the entire range of challenges from user-facing API-s, through high-level algorithms, all the way down to firmware.

The team develops breakthrough next-generation silicon products.

If you're looking to work with outstanding people, developing the first iteration of world-class products, join us!

In this role, you will:

Design and develop data plan software driving the world's most sophisticated infrastructures, using a modern P4 which is a domain-specific language for network devices, specifying how data plane devices (switches, routers, filters, etc .) process packets.

Gain intimate knowledge of world-class silicon and programming models.

Work with architecture and design teams to define the next generation of ASIC products being developed.

Join the PHY system team, a pivotal part of our development. Our team focuses on the PHY and system aspects of our devices, including PHY firmware, calibrations, system definitions, operations, and post-silicon validation.

Key responsibilities include:

Working with the latest silicon technologies and processes to build large-scale, complex devices at the forefront of feasibility.
Contributing to the development of PHY firmware and system calibrations.
Participating in system definitions, operations, and post-silicon validation activities.

What Youll Do:

Youll be part of the group driving next-generation network devices within a startup-like atmosphere inside a well-established, leading corporation.

Our unique design center integrates all silicon hardware and software development disciplines under one roof. We are revolutionizing the industry by building a new internet for the 5G era, with a unified, programmable silicon architecture that will underpin Cisco's future routing products. Our devices are designed for adaptability across service providers and web-scale markets, delivering high speed without compromising programmability, buffering, power efficiency, scale, or feature flexibility.

Join the PHY system team, a pivotal part of our development. Our team focuses on the PHY and system aspects of our devices, including PHY firmware, calibrations, system definitions, operations, and post-silicon validation.

Key responsibilities include:

Working with the latest silicon technologies and processes to build large-scale, complex devices at the forefront of feasibility.
Contributing to the development of PHY firmware and system calibrations.
Participating in system definitions, operations, and post-silicon validation activities.

What Youll Do:

Youll be part of the group driving next-generation network devices within a startup-like atmosphere inside a well-established, leading corporation.

Our unique design center integrates all silicon hardware and software development disciplines under one roof. We are revolutionizing the industry by building a new internet for the 5G era, with a unified, programmable silicon architecture that will underpin our future routing products. Our devices are designed for adaptability across service providers and web-scale markets, delivering high speed without compromising programmability, buffering, power efficiency, scale, or feature flexibility.

We are seeking a CAD Engineer to join the Physical Design team.

You'll be joining our Physical Design team within us, which is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.

Our Backend Engineers handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.

You will be the tech lead for CAD within the team, leveraging your extensive backend and physical design experience to drive the development, optimization, and innovation of CAD methodologies and tools, ensuring the highest quality and efficiency in our chip design flows from RTL to GDS.

We demonstrate the latest silicon technologies and processes to build the largest-scale and most complex devices, pushing the boundaries of feasibility.

Your Impact:

Review micro-architecture specifications.

Supervise verification team members and provide professional guidance.

Implement Verification environment UVM based.

Collaborate with Design engineers to resolve bugs and achieve coverage closure.

Work with the firmware/Lab teams to verify chip flows.

Perform debug, root-cause analysis, and post-silicon validation in the lab.

As part of the Architecture team, you will:
Directs, leads, and manages the technical activities of a hardware development function for electronic design, mechanical design and/or hardware reliability.
Directs, leads, and manages the technical activities of a software development function for software systems, applications and/or software quality assurance.
Directs, leads, and manages the technical activities of an integrated hardware/software systems design function.
Define device specifications and architectural features for next-generation networking silicon.
Design and implement logic and software solutions that meet performance, power, and scalability requirements.
Develop software components in C++ as part of the silicon architecture and enablement flow.
Collaborate closely with design, verification, and software teams to translate specifications into working silicon.
Contribute to the development of a unified and programmable silicon architecture enabling AI-driven networks.
Take part in shaping our products that power the Internet of the future.

As a key member of the team, you will be responsible for developing a state-of-the-art functional simulator for the family of devices. This simulator is a critical product that streamlines the development process and significantly reduces time-to-market.

In this role, you will:

Collaborate closely with the ASIC Architecture team to implement an accurate and efficient software model based on the architecture specifications.

Partner with both Software and Hardware design teams, providing support as they use the simulator as the golden reference for hardware implementation.

Ensure the simulator meets the highest standards of performance, reliability, and usability.

Contribute to defining best practices and methodologies for model development, validation, and integration. 

As a key member of the team, you will be responsible for developing a state-of-the-art functional simulator for the family of devices. This simulator is a critical product that streamlines the development process and significantly reduces time-to-market for our solutions.

In this role, you will:

Work under the guidance of senior engineers to help implement and maintain components of the simulator based on architecture specifications.

Collaborate with the ASIC Architecture, Software, and Hardware teams to understand requirements and support their use of the simulator as a reference for development.

Participate in troubleshooting, testing, and validating simulator functionalities.

Learn and apply industry best practices in model development and integration. 

Your Impact:
Write and review micro-architecture specifications.
Implement RTL (Verilog/SystemVerilog) to meet timing, performance, and power requirements.
Contribute to full chip integration, timing methodology, and analysis
Collaborate with verification engineers to resolve bugs and achieve coverage closure.
Work with the physical design team to close timing and PnR issues.
Support design methodology evolution and best practices.
Perform debug, root-cause analysis, and post-silicon validation in the lab.

Physical Design team within us is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.

We demonstrate the latest silicon technologies and processes to build the largest-scale and most complex devices, pushing the boundaries of feasibility.

Your Impact
You'll be part of the team, which is at the heart of our software and ASIC design efforts.

You'll handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.

As a key member of the team, you will be responsible for developing a state-of-the-art functional simulator for the family of devices. This simulator is a critical product that streamlines the development process and significantly reduces time-to-market for our solutions.


In this role, you will:

As a Senior engineer you will implement and maintain components of the simulator based on architecture specifications.

Collaborate with the ASIC Architecture, Software, and Hardware teams to understand requirements and support their use of the simulator as a reference for development.

Participate in troubleshooting, testing, and validating simulator functionalities.

Learn and apply industry best practices in model development and integration. 

Join the Front-End Design team, at the core of our development. Our engineers cover the full spectrum of chip design: definition, architecture, micro-architecture, RTL design, verification, signoff, and validation.
We leverage cutting-edge silicon technologies and methodologies to develop the largest-scale and most advanced devices, pushing the boundaries of whats possible.
We are transforming the industry with a unified, programmable architecture powering our future routing portfolio and shaping the Internet for decades to come.

Your Impact:

Review micro-architecture specifications.

Implement Verification environment UVM based.

Collaborate with Design engineers to resolve bugs and achieve coverage closure.

Work with the firmware/Lab teams to verify chip flows.

Perform debug, root-cause analysis, and post-silicon validation in the lab.

We are looking for a highly experienced product manager expert to join our Product and Architecture team. The Product & Architecture team is responsible for defining, directing, and driving the product strategy for the entire software stack. If you are a Strategic thinker who can translate market needs into actionable product plans while balancing technical feasibility, an excellent communicator, an Influencer and a negotiator-capable of rallying disparate teams around a common vision and resolving conflicts in a fast‑moving startup environment where priorities shift rapidly, you belong with us.

In this high-visibility and influential role, you will take part in building the process of turning customer requests into shippable action items, working with customers and leaders, scientists and researchers and of course developers and engineers in complex, highly technical domains.

Responsibilities:
Strategic product ownership - research market/HPC needs, set roadmap, and define positioning for the accelerator stack.
Feature prioritization & backlog grooming - write clear user stories, enforce acceptance criteria, and balance short‑term delivery with long‑term performance goals.
Cross‑functional leadership - assist managers in leading sprint planning, reviews and retrospectives; coordinate software, firmware, hardware, and customer‑success teams.
Customer advocacy & feedback loop - capture interview insights, translate pain points into technical requirements, and track feature‑adoption metrics.
Performance KPI management - assist leadership in defining throughput/latency/energy targets, oversee benchmark suites (FFT, BLAS, MPI), and report quarterly results against industry leaders.
Continuous product quality improvement - monitor defect rates, regression test coverage and performance regressions; drive actions that reduce technical debt and increase customer confidence.