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Requirements:
5+ years of experience in high-speed SERDES design, implementation, or research, with hands-on involvement in previous generations of Ethernet standards (e.g., 100G, 200G, 400G).
Proven experience with IEEE 802.3 working groups and standards, particularly in areas related to Ethernet and optical PHY layer technologies (e.g., 802.3ba, 802.3bs, 802.3cd, 802.3ck)
Deep knowledge of modulation techniques such as PAM4 and NRZ, as well as high-speed signaling protocols used in both optical and copper interconnects
Expertise in physical layer research, signal integrity, channel modeling, equalization and error correction techniques for high-speed links
Experience working with key industry players, vendors, and consortiums to shape standards and drive technology adoption
Strong ability to produce technical reports, white papers, and presentations that distill complex technical information into actionable insights
How would you stand out:
Advanced Degree: Masters or PhD in Electrical Engineering, Communications Engineering, or a related field
Expertise and knowledge in in PCS/PMA sublayers, GMII Interface and MAC (Media Access control) in IEEE 802.3.
Extensive involvement in developing Ethernet standards from 100G up to 400G, with insights into the evolution toward 800G and Terabit Ethernet
Demonstrated leadership in managing cross-functional engineering projects related to PHY layer technologies and SERDES interface innovation
Previous experience presenting at or contributing to major industry conferences and events (e.g., OFC, ECOC, IEEE Ethernet Alliance meetings).

Requirements:
- At least 3 years of experience in RF design and optimization
- Excellent understanding of antenna theory (aperture, gain, beam width, dipole vs. isotropic) and antenna performance (return loss, VSWR, etc.)
- Understanding of system topology and air interface parameters of the main telecommunication technologies (GSM, UMTS, LTE, etc.)
- Local Security clearance and Hebrew is a must
- Excellent knowledge of Office tools (Excel, Access,..)
- Experience in Electromagnetic Field evaluation for sanitary perits obtainment is considered an advantage
- Good knowledge of radio equipment is considered an advantage
- Familiarity with automation tools such as Mentum or Planet is considered an advantage
- Excellent analytical and problem-solving skills
- Ability to work independently and as part of a team
- Good communication and interpersonal skills
- Good performance under pressure

Requirements:
Ph.D. or Masters degree in electrical engineering, mechatronics, control theory and engineering, robotics, etc.
Familiar with the principle of permanent magnet brushless motor and voice coil motor; proficient in Matlab, C/C++ or other programming tools.
Previous experience in leading the development of low-level servo drive & controller algorithms and control algorithms in industry-leading drives/controllers.
Previous experience in breakthroughs of key technologies, such as high-precision dual-drive gantry system, high-precision rotor phasing, jittering suppression, automatic identification of motor parameters, etc.
Proficient in common industrial encoder protocols; previous experience in developing servo drive & controller software and hardware; proficient in developing and debugging protocols such as BISS, Endat, SIN/COS.

Requirements:
MSc or BSc in computer science/EE or area related to computer architecture, or equivalent research experience in industry
At least 7 years of relevant research and development experience in industry and academia in the following areas:
Computer architectures: instruction set architecture, microarchitecture, cache sub-system, memory sub-system, NOC, interconnect
Workload characterization and analytical model generation
System Modelling and emulation of HW.
Simulation of Software workloads and Software applications on HW simulator
Ability to provide innovation and global vision throughout the company
Excellent communication, presentation and reporting skills
Experience working with highly technical teams and communicating to non-technical partners.
Excellent oral and written English.

Requirements:
BSc in Electronics Engineering.

10+ Years of industry experience in Design.

Team Player, with excellent interpersonal skills.

Highly Motivated.

Acquaintance with all aspects of chip development.

Micro-Architecture.

Design and verification tools and methodologies.

Experience with Verilog RTL coding and Verification support.

Experience and synthesis flows an advantage.

Working with FW and SW engineers.

Requirements:
Qualifications:

BSc in Electronics Engineering or Computer Science.

10+ Years of industry experience in verification, full chip dev. cycle.

2+ years of experience in leading a team of engineers (including technical and personal mentoring, etc.).

Experience with System Verilog and UVM methodology - MUST.

Hands-on experience with two or more of the following :

PCIE (Gen5 and above).

DDR (v4 and above).

AMBA protocol family, (inc. AXI4+, ACE/CHI)

ARM core architecture.

Advantages:

M.Sc. in Electronics Engineering or Computer Science.

Working experience with Formal verification.

Scripting skills in Python/Perl/shell.

Requirements:
Associate or bachelors degree in Electronics Engineering. Proven experience in VLSI circuit testing, including digital, analog, and mixed-signal circuits. Strong knowledge of VLSI design and testing methodologies. Proficiency in using TEST equipment such as oscilloscopes, logic analyzers, and automated TEST systems. Experience with scripting languages (e.g., Python, PERL) for TEST automation. Excellent problem-solving skills and attention to detail. Strong communication and teamwork skills. Ability to work independently and manage multiple tasks effectively. Preferred Qualifications: Experience with industry-standard EDA tools (e.g., Cadence, Synopsys). Knowledge of semiconductor manufacturing processes and reliability testing. Familiarity with Imaging industry. Benefits: Professional development opportunities and continuous learning. Flexible work hours and remote work options. Collaborative and inclusive work environment. True contribution to future and safety of Israel. Location: SCD Bar-Lev site
Job Type: Full-Time.

Requirements:
B.Sc in Electronic or Mechanical Engineering
3+ years of hands-on experience as managing chip packaging vendors
5+ years of hands-on experiences in chip package activities
Experience with relevant CAD tooling for chip package development & simulation for layout, mechanical & thermal simulations
Experience with Digital High Speed, Analog and Power design
Experience with Signal Integrity and Power Integrity simulation tools for Digital and analog using IBIS and S-Parameters models advantage
Familiar with Automotive industry advantage
Experience with RFIC design and simulation - advantage.