דרושים » הנדסה » Hardware Engineer- HW Board Design

You will own the complete EVB hardware bring-up process from initial power‑on through release to internal engineering teams. This role is highly practical and technical, responsible for identifying and resolving complex board- and ASIC-level hardware issues, documenting findings, and driving corrective actions.

Key responsibilities
Own and execute complete EVB hardware bring-up, validation, and qualification activities in the lab.
Perform initial board power‑up, verify power rails and sequencing, validate clocks and resets, and exercise interfaces.
Lead hands‑on debugging and root‑cause analysis of board‑level and ASIC-related hardware failures.
Read and use complex hardware schematics and PCB layout data as primary debugging tools; review PCB manufacturing data when investigating failures.
Perform detailed lab measurements (oscilloscopes, VNAs, logic analyzers, power supplies, electronic loads) and correlate results with schematics, layout, ASIC requirements, and simulations.
Collaborate with SI and PI teams to investigate signal-quality, channel-loss, reflections, power-delivery, and noise issues.
Work with FPGA and BSP/SW engineers during initial system bring-up and debugging.
Document bring-up procedures, debug findings, measurements, known issues, workarounds, and solutions.
Support manufacturing and assembly debug (PCB, SMT, soldering, component and assembly-related failures).
Drive hardware issues through identification, root‑cause analysis, corrective action, implementation, and final validation.

As SIPI engineer youll be required to design and analyze high speed analog/digital signals for networking products, with emphasis on high speed signal and power analysis of ASIC, Package and PCB. Model/simulate/characterize high speed systems, including high speed I/Os, chip packages, printed circuit boards, and system interconnects. Overcome the challenges of ultra-high data rate and cutting-edge technology. We use the latest silicon technologies and processes to build largest scale and most complex devices at the edge of feasibility.

Lead hands-on lab debugging to fix complex silicon performance, characterization, and yield issues. Use bench findings and board-probing data to give feedback directly to the architecture and design teams. Lead ASIC bring-up on validation boards, focusing heavily on SerDes, high-speed interfaces, and power/clock domains. Run characterization across PVT (Process, Voltage, Temperature) conditions and analyse large datasets to resolve performance bottlenecks and improve chip yield. Write and optimize clean Python code to automate lab equipment and test internal chip logic. Serve as the technical lead for complex hardware debug, defining validation methodologies, and advanced lab measurement techniques for the team.

We are seeking a high-driven, results-oriented multidisciplinary orchestrator to act as the primary catalyst for our development infrastructure. In this role, you will operate at the critical intersection of product strategy, hardware engineering, and lab operations, serving as the connective tissue that aligns disparate teams under a unified goal. You will be responsible for driving cross-functional alignment across the organization, effectively managing stakeholders with differing ownership to ensure infrastructure roadmaps scale alongside product milestones. This position requires a self-starter comfortable pushing for success in ambiguous environments, where you will translate high-level strategy into the tactical execution of the physical and virtual ecosystems that power our development lifecycle.

Your Impact

You will own the end-to-end lifecycle of infrastructure projects, ensuring that our Sanity Test Beds and development environments are optimized to meet aggressive product launch timelines. By bridging the gap between engineering roadmaps and infrastructure requirements, you will serve as the engine that ensures our teams have the right resources at the right time, regardless of technical or organizational complexity.

Key Responsibilities

Strategic Orchestration & Alignment

Unified Roadmap Integration: Translate complex product development roadmaps into long-term infrastructure requirements, driving cross-functional alignment between silicon milestones and lab availability.
Stakeholder Management: Act as the primary liaison between hardware engineering, software development, procurement, and lab operations; navigate competing priorities among stakeholders with differing ownership to keep teams synchronized.
Ambiguity Management: Proactively identify project roadblocks and navigate ambiguous environments to push critical-path dependencies to resolution.
Operational Velocity: Drive continuous improvement in infrastructure processes, identifying and removing friction to increase overall engineering velocity.
Operational Oversight & Execution

Strategic Capacity Planning: Lead high-stakes capacity management efforts, forecasting needs for power, rack space, and compute resources to proactively eliminate infrastructure bottlenecks.
Lifecycle Ownership: Oversee the full lifecycle of infrastructure projects-from initial procurement and technical specification through deployment, validation, and transition to operational readiness.
Visibility & Reporting: Drive the development of dashboards and reporting mechanisms to provide real-time visibility into infrastructure health, ensuring data-driven decision-making across the organization.
Vendor & Asset Optimization: Partner with cross-functional leadership to manage technical specifications, equipment lead times, and hardware lifecycles, ensuring a high-performance, cost-effective infrastructure footprint.

We are seeking a highly skilled Algorithm Engineer with a strong focus on deep learning and problem-solving. The ideal candidate will have proven experience in end-to-end development - from research and prototyping to production deployment - and a passion for applying advanced algorithms to transform the field of medical robotics.

Responsibilities:

Design, develop, and deploy cutting-edge algorithms to enhance the accuracy, robustness, and efficiency of robotic surgical systems.
Apply deep learning, computer vision, and advanced data analysis techniques to solve challenging perception and decision-making problems.
Lead end-to-end development cycles: problem definition, algorithm design, implementation, optimization, and integration into real-time systems.
Collaborate with multidisciplinary teams, including software, hardware, and clinical experts, to ensure algorithms meet system and clinical requirements.
Validate and refine algorithms through simulation, lab testing, and clinical feedback.

In this role, you will be leading all aspects of verification and will have a critical impact on the company's R&D path.



Responsibilities:

Define and implement robust SV/UVM verification solutions, including test benches and methodologies, to drive efficient verification closure across block-level and full-chip designs, integrating Mix-signals SoC simulation environment using Verilog, MATLAB, HW/SW Co-simulation and lab integration.
Work closely with Digital Design, Analog Design, Software, Back-end, SW and System teams to understand the functional, power and performance goals of the product and ensure its quality.

We are transforming the industry and building a new internet for the 5G era, providing a unified, programmable silicon architecture that is the foundation of all future routing products.

Our devices are designed to be universally adaptable across service providers and web-scale markets, designed for fixed and modular platforms. Our devices deliver high speed without sacrificing programmability, buffering, power efficiency, scale or feature flexibility.

Cisco Silicon One is a revolutionary, ground-breaking technology for our customers and end users for decades to come! The Internet now has a new faster, better, safer engine!

Write and review micro-architecture specifications

Implement RTL (Verilog/SystemVerilog) to meet timing, performance, and power requirements

Contribute to full chip integration, timing methodology, and analysis

Collaborate with verification engineers to resolve bugs and achieve coverage closure

Work with the physical design team to close timing and PnR issues

Support design methodology evolution and best practices

Perform debug, root-cause analysis, and post-silicon validation in the lab