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We're looking for a Design Verification Team Lead - a design verification technical lead that is responsible for complex SoC sub-system, with cutting edge technology for Nitro system SoC, the foundation of AWS's virtualization, networking, and storage offload infrastructure.

It starts at product definition - we engage from day one, shaping requirements and translating product intent into verification strategies before a single line of RTL is written.

It extends into software - we work side-by-side with SW teams, verifying hardware-software interfaces and ensuring seamless integration across the stack, with particular emphasis on networking workloads such as ENA and EFA.

It reaches into physical design - we verify physical design aspects within functional verification, bridging the gap between logical correctness and silicon reality.

It closes the loop - from spec to silicon, our verification touches every team and every stage of chip development.

Key job responsibilities

- Develop and execute verification plans for IO sub-systems - covering interconnect protocols, peripheral interfaces, and system-level integration with a strong connection to networking flows (ENA/EFA).

- Verify IO sub-system features, including interconnect protocols and various accelerator engines.

- Develop and debug C embedded SW as part of hardware-software integration verification.

- Build and maintain UVM-based verification environments for various clusters and sub-systems.

- Verify ARM advanced interconnect protocols (AMBA CHI/ACE/AXI) ensuring correct coherency transactions, performance verification, and protocol compliance.

- Verify the IO virtualization SMMU/TLB operations, page table walks, translation granules, and memory attributes (cache-ability, share-ability).

- Develop constrained-random and directed test strategies targeting corner cases in IO protocol hazards, coherency races, and system boundary conditions.

- Drive coverage closure using functional coverage models, assertion-based verification, and formal methods where applicable.

- Contribute to performance verification - ensuring micro-architectural implementations meet performance targets alongside correctness.

We are looking for a Nitro System Manufacturing Integration Lead Engineer to be part of defining, shaping, and implementing manufacturing flows, test definitions, and card-to-server integration processes for Nitro-based platforms. This includes to be part of the manufacturing flow architecture, production test strategy, process stabilization, and yield optimization bridging system design intent with high-volume manufacturing execution.

Key job responsibilities
As a System Manufacturing Integration Lead Engineer, in the Nitro team, you will own the end-to-end manufacturing flows for accelerator card-to-server integration across manufacturing partner facilities driving the process from initial definition through stabilization into a scalable, high-yield mass production operation.

Key responsibilities include:
- Architect manufacturing flows - be part of the complete card-to-server integration sequence, including every process step, quality gate, and decision point from sub-assembly through system integration and tests.
- Define test strategy - be part of determining what to test, when, and at which station, covering card-level functional tests, post-integration validation, firmware provisioning, and first power-up diagnostics.
- Establish classification criteria - be part of determining pass/fail thresholds and test exit gates to maximize yield and minimize material waste.
- Drive process stabilization - work directly and on-site with manufacturing partners to implement, debug, and iterate on manufacturing flows from early builds through a locked, repeatable production process.
- Design alternative flows - develop parallel manufacturing paths to address real-world constraints such as component availability gaps, deferred card integration, and hub-based assembly models.
- Own process documentation & KPIs - maintain manufacturing flow baselines, drive process change control, and track yield, first-pass rate, cycle time, and defect Pareto.
- Lead cross-functional coordination - serve as the single point of ownership across hardware engineering, firmware, test/vetting, thermal, mechanical, and operations teams for Nitro-based accelerator servers built at scale.

Were searching for a Lab Technion Student who will be responsible for the installation, configuration, maintenance, and troubleshooting of our Linux-based server infrastructure, as well as managing various network services and components.

Student will have at least 4 semesters remaining in their degree. The ideal candidate will posses a strong passion for learning new things and the ability to quickly put that new knowledge and skills into practice. You will have the ability to perform basic troubleshooting for hardware, software, and networking issues without guidance.

We're looking for Electrical Engineering graduates to join the Pre-Silicon Verification Team based in Haifa.

As a Junior Pre-Silicon Verification Engineer, you'll work at the heart of chip development, collaborating across teams to ensure our semiconductor platforms meet the highest standards before they reach production.
IO verification team will expose you to the most advanced technologies , as we lead the market with our leaving devices - youll soon have to expertise most advance protocols

A day in the life
In this role, you'll engage in pre-silicon verification work that connects every phase of our product development journey- from initial product definition through firmware and software development.
You'll collaborate with hardware designers, software engineers, and cross-functional teams to validate complex semiconductor architectures and protocols.
Your days might include developing and executing verification test plans, analyzing simulation results, troubleshooting design issues, and participating in design reviews.
You'll work with advanced verification methodologies and tools, gaining exposure to cutting-edge technologies that define the next generation of cloud infrastructure.

We're looking for exceptional engineers to join our Signal/Power-Integrity and Packaging team. A team that sits where the Silicon meets the Board, bridging the gap between what happens internally at the DIE and the overall system interconnect and the external memories and peer devices.
What sets us apart:
Small team, yet a one stop shop for IP electrical integration at the DIE level, Package design, SI/PI simulations, Layout, Board-design and advanced lab characterization.
Combining Signal-Integrity and Layout, to come up with optimized Package and PCB designs.
Holistic view of the entire interconnect, from the DIEs metals, through the Package, to the PCB traces, and all the way to the peer device.
In-depth post-silicon characterization, using advanced measurement techniques, far exceeding traditional compliance measurements.
Deep dive mentality, in both theory and the bolts and nuts that make the internal circuitry of the electrical interfaces.

The SIP (Signal-Integrity & Packaging) team is part of Annapurna-Labs Chip development team.
The team is dealing with the external electrical interfaces of the device, from their Signal/Power-integrity and electrical usage perspectives.
The teams work includes close work with the BackEnd team on integrating these interfaces to the Die, the package layout design of the BGAs substrate, Signal and power integrity simulations, and working with the system team to come up with optimal pin-out and optimal PCB breakout schemes.
We are looking for highly motivated Electrical Engineering graduates, or engineers with up to 3 years' experience in related fields, to join our growing team specializing in Signal Integrity and IC Package Design. The position offers a unique entry point into a diverse and multidisciplinary domain.

Key job responsibilities
Work on advanced high-speed interfaces such as PCIe, DDR and Ethernet.
End-to-end solution of high-speed interfaces; from floor-planning at the DIE level, through Package and PCB routing, addressing both robust SI/PI considerations as well as optimizing layout routing.
Signal and power integrity modeling and simulation of high-speed interconnects using advanced SI/PI simulation tools.

Were searching for sharp engineers to lead cutting edge products, re:inventing super computers and deploy our new SRD (Scalable Reliable Datagram) network protocol into the largest public cloud on the planet! starting from the identification and definition of project requirement, defining SW and HW interfaces, feature development and deployment, to operation support on a very large scale.

We are developing leading edge products, manufactured on leading edge technologies. We offer a dynamic, open, teamwork environment operating at high pace mode.

Key job responsibilities
Primary responsibilities:
- Development of DfX (DfM, DfT, DfQ&R, etc.) methodologies and BKMs (Best Known Methods).
- DfX activities during the product design stage.
- Product quality & reliability validation (QRV) and ongoing quality & reliability monitoring (OQRM).
- Q&R engineering of volume manufacturing: auditing, monitoring, risk assessment and disposition of non-conformance events/non-conforming material, defining and implementing corrective actions.
- RMAs: investigation, disposition, reporting and follow-up.

We are developing leading edge products, manufactured on leading edge technologies.
We offer a dynamic, open, teamwork environment operating at high pace mode.

Key job responsibilities
Assume full ownership of mechanical and thermal design of Annapurna ICs.
Engage with product architect and design teams on future products package and assembly needs
Perform package level thermal simulations.
Perform package level mechanical simulations.
Lead and design thermal and mechanical measurements of ICs.
Explore and provide recommendations on both available and future packaging and assembly technologies for Annapurnas products.
Engage with substrate and assembly vendors on future technologies roadmap.
In collaboration with HW Dev team optimize mechanical vs. thermal tradeoffs.
Ensure testability of the ICs in collaboration with Test Engineer team.

We are looking for an Embedded Software Engineer to join the SW group and take a major part in redefining the future of AWS cloud.

Were searching for engineers with a passion for networking to develop SRD (Scalable Reliable Datagram). SRD is a high-performance, low-latency transport protocol used within our Web Services infrastructure to optimize network performance. SRD powers several high-impact, cutting-edge products, including on-demand ML and HPC platforms leveraging EFA, next-generation storage services built on EBS, and the future of AWS network traffic.

Key job responsibilities
As an Embedded Software Engineer on the SRD team, your primary responsibility will be to develop and optimize SRD technology across AWSs network infrastructure. You will work on cutting-edge, high-performance platforms that power ML, HPC, and storage-intensive workloads.

Your role will involve designing, deploying, and maintaining the SRD codebase, ensuring its reliability and scalability to meet the demands of diverse applications. You will gain in-depth knowledge of the various platforms and services running SRD within AWS, diving deep to understand their unique challenges and complexities.

Collaboration will be key, as you will work across multiple teams at different layers of the software stack. You will also contribute to defining new hardware modules and enabling offloads to enhance performance.

As a Software Development Engineer in Test on our team, you will own the quality of Nitro card embedded software and firmware. You will design, develop, and maintain test automation for embedded systems and components, covering hardware interface verification, real-time firmware behavior validation, firmware update integrity, and fleet-scale deployment confidence. You will collaborate closely with firmware development teams to troubleshoot complex system-level problems at the hardware-software boundary and ensure timely delivery of high-quality Nitro card software to AWS Cloud solutions.

Key job responsibilities
- Own the firmware test automation framework - architect, develop, and extend a Python-based validation solution that scales across multiple Nitro card generations and hardware platforms, automating test coverage across the full firmware stack from boot sequences through board management layers and card-level system integration.
- Design and implement traceable, specification-driven test cases that validate firmware functional correctness, fault tolerance, and performance across hardware components, communication interfaces, and cross-subsystem interactions.
- Optimize CI/CD pipelines by integrating pre-merge and post-merge firmware validation, defining trigger policies per hardware generation, enforcing coding-standard compliance, and reducing commit-to-validated cycle time.
- Troubleshoot complex embedded system failures by analyzing firmware logs, system traces, and hardware diagnostics, then translate field incidents into targeted regression suites that prevent recurrence.
- Collaborate with firmware and hardware teams during new-generation silicon bring-up, define test plans, drive quality gates for production release, and mentor teammates on testing best practices and system architecture.

A day in the life
You start your morning reviewing overnight CI results and triaging any firmware validation failures flagged across active Nitro card generations. Mid-morning, you pair with a firmware engineer to debug a boot-sequence regression discovered during pre-merge testing, using hardware-in-the-loop test benches and system traces. After lunch, you join a design review for a next-generation Nitro card, providing input on testability and proposing validation strategies for new subsystem interfaces. Later, you refine your test framework to improve coverage for a recently released feature, then wrap up by sharing your findings in a team knowledge-sharing session.

We are looking for talented engineers to help us develop the semiconductor platform which is based on revolutionary architecture.
Take part in the development of cutting edge products within disruptive system architecture. Youll have the opportunity to work on the technologies that power the worlds largest Cloud provider, within a dynamic, open, and fast-paced environment. Amazon Web Services provides a highly reliable, scalable, low-cost infrastructure platform in the cloud that powers hundreds of thousands of businesses in 190 countries around the world.

Exciting opportunity to join Amazon in developing its next generation products for the cloud market.
We are looking for talented people to join the team and help us technically lead the challenges of the next decade.
In this job you will be exposed and learn wide range of expertise such as: C++ programing, hardware design, data mining, Verilog simulations, working with various high end test equipment and more
If paving new roads on edge of technology within a strong and vibrant team is what you seek, your place is with us.

The Labs Security Team secures the firmware at the foundation of our custom silicon. We work on Graviton processors and the Nitro System - hardware that runs a substantial share of the world's cloud workloads - in close collaboration with the silicon architects and firmware developers who design it. Our engineers operate at the lowest levels of the stack: secure boot chains, hardware root of trust, attestation, cryptographic protocol design, and the boundaries between trust domains within the system.

Key job responsibilities
As a Security Engineer, you will threat model new silicon and firmware architectures, conduct low-level penetration testing against privileged and externally reachable interfaces, review designs and code across multiple firmware components, and build the fuzzing and analysis tooling that makes this work repeatable at silicon scale. You will also help raise the security bar across the wider organization through direct engagement with firmware and hardware teams. We are looking for engineers fluent in C and ARM assembly, with real depth in secure boot, applied cryptography, or embedded exploitation, and the technical credibility to hold a position in a room full of people who designed the system you are testing.

As HW Validation student in the Nitro team you will be responsible to validate the hardware of our network interface card (Smart NIC).
Youll provide leadership in the HW interfaces of new technologies to large scale deployments in a continuous effort to deliver a world-class customer experience. This is a fast-paced, intellectually challenging position, and youll work with thought-leaders in multiple technology areas.

Key job responsibilities
- Own hardware validation activities for our products, from test execution through analysis and debug.
- Analyze validation and production data to identify issues, trends, and opportunities for improvement.
- Collaborate with HW, SW, and validation teams to enable efficient testing, debug, and issue resolution.
- Develop and execute validation and performance tests, considering both technical requirements and customer needs.
- Support the validation and deployment of new hardware technologies at scale.

We are looking for a Senior Product IC Q&R Engineer to join the team and lead the Q&R activities for our Nitro and Graviton product lines which enable the success of AWS.
As a senior product IC Quality and Reliability Engineer, you will play a crucial role in ensuring Annapurna Labs' semiconductor products meet customer demands. Your responsibilities will include establishing Design-for-Quality and Reliability (DFQR) during product design, developing reliability validation (RV) plans and DOEs, conducting product qualification and RV, support debug of qualification failures, and executing reliability modeling, analysis, and reporting.
In this role you will have end-to-end exposure to Annapurna's products, from semiconductor production flows and semiconductor testing methodolorgies to the operation of these products in the field.

Key job responsibilities
You will work with the design team to implement DFQR (design for quality and reliability) and DFRT (design for reliability testing) requirements for Annapurna Labs products.
You will evaluate Q&R risks, prepare reliability validation plans to mitigate them and work with multiple stakeholders to execute the reliability validation for Annapurna Labs products.
You will support Annapurna Labs production by qualifying new technologies, vendors and materials which enables Annapurna Labs leadership in AWS datacenters.