לוח משרות דרושים מהנדסים

We are looking for a motivated and experienced Full-Stack Engineer with 3+ years of hands-on experience to join one of our teams. As a Full-Stack Engineer , you will take ownership of features across the entire development lifecycle - from initial concept and design to deployment and maintenance in an enterprise-grade production environment. This role involves close collaboration with the product team to turn ideas into high-quality, functional software.

Responsibilities:

Develop and lead the end-to-end implementation of new features and product offerings
Design, build, and maintain efficient, reusable, and reliable code across the full stack
Collaborate with UI/UX designers, product managers, and engineers
Participate in all phases of the development lifecycle, including analysis, design, coding, testing, and deployment
Ensure application performance, quality, and responsiveness

As a Research Engineer , you will design, develop, and implement algorithms and models that will enhance the products capabilities, performance, reliability, and scalability. Together with our algo and engineering team members, you will work closely with our product team members to implement algorithms that can be used to drive our business forward as well as the frontier of software development AI technologies.

Responsibilities:

Design, develop, implement and test algorithms and AI-empowered solutions for various product features and applications
Collaborate with cross-functional teams to understand business needs and translate them into algorithmic solutions
Perform research on emerging trends, algorithms, and cutting-edge technologies, and identify ways to incorporate them into our products pragmatically
Propose new and innovative solutions to complex problems and lead the development of algorithms in those areas
Design, cleanse, and utilize benchmarks throughout the process of the algorithm development

We are looking for a skilled QA Automation Engineer (backend oriented) to join our Parking domain. You will play an important role in ensuring the quality of mission-critical systems that serve millions of users daily.
The majority of the role is automated testing combing AI Skills but combines manual as well.
This is a great opportunity for somebody who want to enhance infrastructures, develop in engineering and great best practices and handle scaled distributed systems based on AWS.
Responsibilities
Design and develop automated tests end to end for new and existing features, execute mainly Backend orientation API tests, including automation for backend services.
Apply AI tools (e.g., Cursor, Claude Code) in day-to-day work to generate code, build automation, and continuously improve testing workflows.
Write and maintain detailed test cases and documentation.
Identify, record, and track software defects and issues, ensuring timely resolution.
Work with tools such as Qase.
Collaborate with cross-functional teams to understand product requirements and design effective testing strategies.

We are seeking a Solutions Engineer to become an integral part of its team, dedicated to offering technical guidance and assistance. The ideal candidate will have the chance to cultivate connections with pivotal clients and play a crucial role in advancing the sales of our products. If you aspire to collaborate closely with our sales, product and R&D team, delivering technical expertise, demonstrations, and solutions to our customers, we would love to hear from you!

What will you do?

Providing technical guidance and support to prospects and customers
Explaining products and services to customers and work closely with them to understand their technical requirements and translate them into effective solutions.
Assisting with product demonstrations, presentations and webinars.
Provide training to clients, both in person and remotely, to ensure they can effectively use our products.
Respond to technical inquiries and provide in-depth information to clients.
Support the closing of deals by addressing technical concerns and objections.
Gather feedback from clients and the sales team to help improve our products and services.

Tavily team is building the search engine for AI agents. We believe the future of work will be led by AI agents, and that requires restructuring how the web is accessed. Our Search API provides web access for AI agents, enabling real-time internet search optimized for LLMs and Retrieval-Augmented Generation (RAG). We are backed by leading investors and serve developers and enterprises worldwide. Our team is fast-moving and ambitious. We ship quickly, iterate constantly, and care deeply about impact.
As a Software Engineer - Scraping Specialist, youll build the systems that power how AI interacts with the live web. Youll design and implement large-scale, intelligent web acquisition pipelines, making sense of an ever-changing online ecosystem and transforming it into structured, high-quality data.
This role blends technical understanding of browsers, networks, and automation with hands-on engineering. Youll work on adaptive systems that navigate modern websites, understand evolving web interaction ,detection systems, and gather meaningful information safely, efficiently, and at scale.
Your work will directly shape Tavilys ability to provide AI agents with accurate, real-time knowledge of the world , bridging the gap between the open web and intelligent reasoning.
What Youll Do
Build distributed data acquisition systems that capture and structure the live web
Investigate and analyze browser internals, fingerprinting, and anti-automation systems to develop stealthy, adaptive orchestration layers
Prototype and deploy intelligent automation frameworks using Playwright, Puppeteer, and low-level browser control protocols (CDP)
Conduct hands-on research into network flows, JavaScript-based protections, and emerging web standards affecting automation
Collaborate with AI and infrastructure teams to integrate real-time web data into retrieval pipelines and LLM-powered agents
Translate deep technical insights into production-grade components, balancing research freedom with engineering rigor
Continuously evolve Tavilys capabilities in resilience, speed, and authenticity of web interaction.

At our company we are passionate believers in the value and power of 3D printing, and in the change, it can bring to design, innovation and manufacturing.
The solutions we create are used by over 20,000 enterprises worldwide, and we literally are shaping the world that surrounds us - from the products and services in our lives and homes, to our health and quality of life, our transport, security and economies, to how we teach, research and even learn.
we are the world's largest 3D printing solutions company - a company at the forefront of 3D printing innovation for more than 25 years.
Who are we looking for?
We are looking for an intelligent, well-rounded and enthusiastic Algorithm Engineer to participate in the design, development and delivery of our innovative software solutions.
The position is based in our Rehovot, Israel headquarters.
If you can operate in a team but also a motivated individual, read on
Remember that exact job descriptions never fit the bill 100% - if youre good, passionate and love to build great products, we want you.
We see your role as
Developing the infrastructure and framework for a highly scalable, Image Processing/geometry ( OpenCV, Ipp) component of a large software product.
Designing and delivering CAD to Print algorithms
Developing geometry-oriented software
Being a part of a talented team.

We are looking for a highly skilled SW developer Expert with substantial Object-Oriented experience in a multi-disciplinary environment to join our R&D group in Israel (Rehovot).
You will be a part of a talented software team that is currently developing the next generation of 3D printers, using cutting-edge technology and constantly looking for new ideas and improvements.
What you will be doing:
Lead development tasks through all stages - gathering requirements, designing, implementing (mostly using C++ and C#) and following integration on the 3D printers themselves.
Work closely with System and HW engineers, SW developers, QA and many more.
Perform design and code reviews
Constant collaboration and knowledge sharing with the SW team.

As a Design Verification Manager for the IP Group, you will lead a focused team responsible for the quality and reliability of our critical IP blocks. You will steer the IP verification roadmap, oversee the development of complex testbenches, and ensure our next-generation AI silicon meets the highest standards. Leading a team of talented engineers, you will tackle challenges at the unit and sub-system levels, playing a pivotal role in delivering high-performance hardware for the worlds largest AI clusters.

Key Responsibilities



Lead and mentor a team of design verification engineers, defining the technical roadmap and methodology for ASIC verification across unit and IP/sub-system levels
Drive the creation and execution of comprehensive design verification plans, ensuring all functional requirements are met on schedule for complex digital IPs
Oversee the architecture and maintenance of block-level verification strategies, heavily utilizing SV-UVM, alongside Formal Verification where applicable
Define functional coverage goals and quality metrics, driving the IP team toward 100% verification closure and sign-off
Partner closely with IP Design and Architecture teams to align on specifications, root-cause complex bugs, and optimize the IP development cycle

As an Expert EMIR & Power Integrity Lead, you will be a core technical contributor ensuring the power robustness and long-term reliability of our high-performance connectivity silicon. You will own from block level to full-chip the Electro-Migration and IR Drop (EMIR) methodology, analysis, and sign-off, working at the intersection of Physical Design, Analog/Mixed-Signal design, and Package Engineering.

You will be responsible for defining power grid architectures and validating that products meet aggressive voltage drop and reliability targets in advanced FinFET process nodes. Your work will directly impact the performance and yield of chips operating in the worlds most demanding AI and cloud environments.

Key Responsibilities

Lead static and dynamic IR drop analysis, signal/power electromigration (EM) verification, and self-heat analysis from block level to full-chip sign-off
Define and implement robust EMIR flows and methodologies using industry-standard tools (Ansys RedHawk-SC, Cadence Voltus, or equivalent)
Collaborate with Physical Design teams to define optimal power grid structures, via pillars, and strap distributions to minimize voltage drop while maximizing routing resources
Work closely with Analog/SerDes designers to analyze current profiles and ensure robust power delivery to sensitive high-speed IP blocks
Partner with Package Design engineers to perform Chip-Package-System (CPS) co-analysis, optimizing bump patterns and package routing for superior Power Integrity
Drive root-cause analysis for voltage drop violations and EM risks; propose and implement layout fixes alongside the PD team
Verify current density rules for ESD protection networks and ensure compliance with foundry reliability constraints
Support silicon bring-up by correlating simulation results with actual silicon measurements and yield data

we are leading the global shift to additive manufacturing with innovative 3D printing solutions for industries such as aerospace, automotive, consumer products and healthcare. Through smart and connected 3D printers, polymer materials, a software ecosystem, and parts on demand, our company solutions deliver competitive advantages at every stage in the product value chain. The worlds leading organizations turn to our company to transform product design, bring agility to manufacturing and supply chains, and improve patient care.
As part of this role you will:
Provide on‑line engineering support and resolve mechanical/technical issues fast.
Improve yield, cycle time, labor efficiency, and overall production performance.
Maintain and optimize work instructions, documentation, tooling, and fixtures.
Support NPIs/EOL and collaborate with cross‑functional teams, subcontractors, and partners.
Reduce rework and scrap and lead second‑source qualifications to strengthen quality and supply resilience.

we're seeking a visionary Expert IC Package Design Lead to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, leading the physical implementation strategy for chips that power the world's largest AI clusters.

As an Expert IC Package Design Lead, you will be a core technical contributor in the development of advanced IC packaging solutions for high-performance connectivity silicon.
You will own package flow, architecture, design, and qualification from concept through production, working closely with silicon, signal integrity, power integrity, mechanical, manufacturing, and external OSAT partners.You will be responsible for defining package technologies that meet aggressive electrical, thermal, mechanical, and cost targets, enabling products to operate reliably in the worlds most demanding AI and cloud environments.

Key Responsibilities

Own end-to-end IC package design, from early architecture and feasibility through detailed design, qualification, and high-volume manufacturing
Define package architecture and technology selection (organic substrates, advanced laminate, interposers, multi-die/chiplet packaging, CoWoS - 2.5D/3D integration)
Lead signal integrity (SI), power integrity (PI), and thermal considerations at the package level for high-speed, high-power devices
Drive package layout, substrate routing, bump/ball maps, stack-ups, materials selection, and mechanical constraints
Collaborate closely with silicon design, SerDes, system, SI/PI, and reliability teams to optimize overall product performance
Interface with OSATs, substrate vendors, and manufacturing partners to ensure design-for-manufacturability (DFM), yield, and cost targets
Lead package-related risk assessment, failure analysis, and corrective actions during bring-up and production ramp
Support NPI, qualification, and product sustainment activities, including vendor audits and technical reviews

As the Physical Design Chip Top Expert you will be a Key member of our PD Team in Israel R&D center. You will run PD execution of SoC Top level for chips that drive the worlds largest AI clusters. As PD Top Level Lead, you will own all PD disciplines of the Chip and own the T.O GDS that meet the chip signoff Criteria (Timing, LVS, EMIR, DRC, PV etc. ) ensuring our silicon meets the extreme performance, power, and area (PPA) targets required for AI scale.

Key Responsibilities

SoC Top level Ownership and oversee the Chip convergence.
Take full ownership of Top Level physical implementation, including floor planning, P&R, CTS, Power/Clock distribution, Power integrity and Timing/Physical signoff
Work closely with the Architecture, Design, DFT, and Product teams to achieve optimal Power Performance Area (PPA). This involves conducting feasibility studies for new architectures and optimizing runs to ensure the best Quality of Results (QoR)
Address complex signal integrity, thermal, and power challenges inherent in high-speed connectivity silicon
Work Closely with Package team on Bump map to Ballout taking into consideration all Signal integrity aspects

As a Physical Design CAD Lead, you will be responsible for the physical implementation environment. Your primary mission is to build, optimize, and support the automated flows from RTL to manufacturable GDSII tape-out. You will own the flows, Database and will support the whole PD team to optimize their blocks for Power, Performance, Timing while keep the team aligned on Methodical, Efficient and balanced work Environment.


Key Responsibilities

Design and maintain automated flows for Synthesis, Place & Route, and Floor-planning
Develop robust environments for Static Timing Analysis, Power Analysis, and Physical Verification (DRC/LVS/ERC)
Write custom plug-ins and scripts to extend the capabilities of vendor tools, tailoring them to our specific process node constraints and flows
Create automated "dashboards" and feedback loops to help design teams track and improve Power, Performance, and Area metrics across iterations
Collaborate with EDA vendors (Synopsys, Cadence, Siemens/Mentor) as consulters for our developed flows and results analysis     

we're seeking a visionary Physical Design Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the backend execution and methodologies for chips that power the world's largest AI clusters.

As a Physical Design Engineer, you will be a key architect of our silicon's physical reality. You won't just execute a flow-you will help establish our local execution culture and technical standards, owning the transformation of complex logic into high-performance silicon. You will drive the physical implementation journey from synthesis through signoff, ensuring our connectivity solutions meet the extreme performance, power, and area targets required for next-generation AI infrastructure. If you thrive on solving complex challenges in deep-submicron processes and want to shape the backend methodology for AI infrastructure connectivity, this is your opportunity.

Key Responsibilities

Physical Implementation & Execution

Be part of the founding Backend team in Israel, playing a critical role in establishing local execution culture and technical standards
Take full responsibility for physical implementation journey including Synthesis, Floorplanning, Place & Route, and Clock-Tree Synthesis (CTS)
Own macro-level implementation with deep hands-on experience in floorplanning and complex routing
Signoff & Design Integrity

Drive final stages of design integrity, owning Timing signoff (STA), Physical Verification (DRC/LVS), and Reliability analysis (EMIR)
Ensure first-pass silicon success through rigorous signoff flows and analysis
Apply Logic Equivalence Checking (LEC) and other verification techniques to guarantee design correctness
Methodology Development & Cross-Functional Collaboration

Participate in defining and refining Backend methodologies with autonomy to improve workflows and tool automation
Work closely with Architecture, Design, and DFT teams to navigate challenges of advanced process nodes and high-speed connectivity
Leverage scripting and automation to make engineering environment faster and more robust