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we are looking for a Graph Compiler Software Senior Team Leader.
As a Graph Compiler Software Manager, you will lead the development of next-generation graph compiler technology. This compiler is a cornerstone of AI software offering, empowering customers to optimize, map, and execute complex neural networks across architectures with extraordinary efficiency. You will lead a group of talented engineers and team leaders working across domains such as compiler optimizations, graph-level transformations, operator mapping, scheduling, and code generation. We are seeking a visionary and technically strong leader with passion for excellence and impact in one of the most fascinating areas of AI and deep learning.
Key Responsibilities:
Lead the design and implementation of innovative graph compilation flows for AI workloads, from high-level optimizations to hardware-specific backends. Build and guide a strong, innovative, and results-driven compiler team that thrives on solving complex technical challenges. Collaborate with hardware architecture, VLSI, and software framework teams worldwide to ensure seamless integration and maximum performance. Lead the end-to-end delivery of graph compiler components while meeting aggressive KPIs. Establish and execute group planning processes to ensure timely and high-quality delivery. Provide technical and managerial guidance to team leaders and engineers. Define and drive compiler optimization strategies for AI and deep learning workloads.

We are looking for a hands-on leader to head a small team that builds simulation models for our next-generation AI hardware and DSP. Modeling is done in several layers, from cycle-accurate, bit-exact block level modeling, to event-driven full IP system flows.
Your groups mission is to take part in the exploration phase of a project, giving architects rapid, high-fidelity feedback so they can explore design options, and to perform algorithmic regression, detecting deadlocks, sweep parameters and features, and understand system-level impact in a quickly adapting, dynamic development environment.
Beyond pure performance modeling, youll keep a sharp eye on functional accuracy and QA, follow emerging academic and industry trends, and inject the relevant insights into the product.
You will also champion modern AI-assisted coding tools (e.g., Cursor AI, GitHub Copilot) to lift the productivity of the senior software engineers on your team and shorten iteration cycles.
Responsibilities:
Lead and mentor a team of simulation and modeling engineers; set goals, review designs, and remove roadblocks. Design and implement transactional / cycle-accurate / bit-exact / event-driven models that faithfully represent advanced AI IP blocks (Transformers, CNN accelerators, custom DMA, interconnects, power-management units, etc.). Build automated flows to sweep architectural parameters and features, collect metrics, and visualize system-level impact on performance, area, power, and bandwidth. Analyze and debug complex issues such as deadlocks, race conditions, and performance hotspots; deliver concise root-cause reports and actionable recommendations. Collaborate daily with architecture, VLSI, compiler, and firmware teams to translate new algorithms and hardware ideas into model requirements and specifications. Own accuracy and QA of the simulation stack: golden-model alignment, coverage tracking, regression health, and release sign-off. Continuously survey academic papers and industry trends, extract meaningful insights, and propose innovative modeling techniques or architectural directions. Promote the adoption of AI-powered development tools to accelerate coding, code-review, documentation, and test generation across the team.

Ready for an intellectual challenge that combines Mathematics and CS theory in the context of hardware development? Keep reading.

In this role you will be responsible for developing mathematical proofs using model checking tools, to find RTL(Verilog) bugs or prove their absence

Not in the Formal domain? No worries, we offer thorough training to learn the theory and practice directly from our team experts.

In this role you will be responsible for developing mathematical proofs using model checking tools, to find RTL(Verilog) bugs or prove their absence .
The position is relevant for both Herzliya/ Haifa site.

we are looking for a R&D Project Manager.
In this role, you will be managing the MBBU projects involving multiple domains including: VLSI architecture, VLSI Design, VLSI verification, VLSI backend, Algorithms and Software. These projects include development of products like cellular modems, Communication Digital Signal Processors and Radar/Lidar baseband with a total of up to 100 R&D engineers involved.
This role is reporting to the MBBU General Manager.
Responsibilities :
Full ownership on all R&D projects of the Mobile Business Unit, including Software, VLSI and Algorithms tasks.
Direct management for the PMO

We are seeking a visionary Director of Engineering with a strong product mindset to lead the strategy, development, and scaling of our Software Supply Chain security product. As a Director of Engineering, you will lead teams building an enterprise-grade Software Composition Analysis solution, meeting the growing needs of our customers and supporting the ever-evolving development ecosystem.
As a Director of Engineering at our company, you will.
Build, lead, and mentor multiple cross-functional teams of developers to deliver a scalable and reliable product
Foster a culture of collaboration, automation, and continuous improvement within the engineering organization
Define and implement procedures and workflows, enabling rapid innovation alongside ensuring enterprise-grade quality of the delivered product
Architect and deliver an enterprise-grade solution that operates in both SaaS and self-hosted environments
Partner with engineering leaders, product teams, and business stakeholders to ensure successful product adoption by the customers.

In your role as a senior PHY Algorithms Development Engineer, as part of our Connectivity Group, you will be part of a world-class group that pioneers design and development of Physical Layer algorithms for wireless communication systems for our products. We live in a mobile and device driven world where knowledge of the physical world around us is needed. We rely on this knowledge to get around, to learn about our environment and to enable spectacular new features for custom applications. We are meeting those needs as robustly and as creatively as possible and is interested in people who want to help meet that commitment. The success we are targeting will be the result of very skilled people working in an environment which cultivates creativity, partnership, and thinking of old problem in new ways. If that sounds like the kind of environment that you find intriguing, then let's talk.

We are looking for a candidate who can innovate and integrate signal processing technologies for solving novel and diverse sets of problems in various wireless communication and sensing technologies:
- Develop communication signal processing algorithms for best-in-class implementation of various wireless standards.
- Conduct basic research of existing solutions in literature.
- Involvement in block level spec definition.
- Perform mathematical analyses of the given problem and its proposed solutions.
- Implement floating-point simulations to prove spec compliance of suggested solutions.
- Implement fixed-point modeling and simulation to allow performance sign-off and RTL bit-exact development .
- Write detailed design documents that will enable implementation of algorithms by other teams specializing in either RTL design or DSP firmware coding .
- Optimize and fine-tune the system for spec compliance on silicon in an RF lab environment.

we are looking for a Senior Communication System and Algorithm Engineer.
In this role, you will engage in developing and implementing cutting-edge 5G technology and products.
Responsibilities:
You will be part of a team responsible for developing 5G modem with: 5G algorithms, 5G SW stack and HW modules, working closely with VLSI and SW teams. Excellent understanding of the cellular standards and the driven implications on Modem design. System and Algorithmic research considering the trade-offs between DSP/SW/HW, performance, implementation cost, real-time, and time-to-market. Managing system definitions, requirement and implementation from research to simulation level to an official release, including MATLAB/C/C++/System C modeling and specification document.

We are looking for an experienced Site Reliability Engineer to help establish and scale SRE practices at our company. You will work closely with R&D and technical leads to improve the reliability, observability, and operational maturity of our production environments. You will lay the foundation for the SRE function-designing alerting standards, building playbooks, and driving automation-while proactively identifying opportunities to strengthen our cloud and Kubernetes based infrastructure.
What will you do:

* Monitor and support production cloud and Kubernetes environments, ensuring high availability and reliability
* Work alongside R&D teams to design and implement actionable alerts
* Fully integrate monitoring and alerting into a centralized incident management platform (e.g., PagerDuty, OpsGenie)
* Create and maintain runbooks and playbooks to automate responses to known failure scenarios
* Improve observability across services using metrics, logs, and alerts
* Identify reliability gaps and recommend infrastructure and architectural improvements
* Enable R&D teams to operate more efficiently through tooling, automation, and SRE best practices

About Us:
we are a leader in threat detection and response, designed to simplify security for organizations of all sizes. Our mission is to empower lean security teams and their partners with an AI-powered, unified platform that autonomously detects, protects, and responds to threats - backed by 247 security experts. With a Partner First mindset, we focus on helping customers and partners stay protected, operate confidently, and achieve their goals. Our vision is to give every organization true cybersecurity peace of mind, providing fast, accurate protection without the noise or complexity.

In your role as a senior PHY Algorithms Development Engineer, as part of Apple Connectivity Group, you will be part of a world-class group that pioneers design and development of Physical Layer algorithms for wireless communication systems for Apple products. We live in a mobile and device driven world where knowledge of the physical world around us is needed. We rely on this knowledge to get around, to learn about our environment and to enable spectacular new features for custom applications. Apple is meeting those needs as robustly and as creatively as possible and is interested in people who want to help meet that commitment. The success we are targeting will be the result of very skilled people working in an environment which cultivates creativity, partnership, and thinking of old problem in new ways. If that sounds like the kind of environment that you find intriguing, then let's talk.

We are looking for a candidate who can innovate and integrate signal processing technologies for solving novel and diverse sets of problems in various wireless communication and sensing technologies:
- Develop communication signal processing algorithms for best-in-class implementation of various wireless standards.
- Conduct basic research of existing solutions in literature.
- Involvement in block level spec definition.
- Perform mathematical analyses of the given problem and its proposed solutions.
- Implement floating-point simulations to prove spec compliance of suggested solutions.
- Implement fixed-point modeling and simulation to allow performance sign-off and RTL bit-exact development.
- Write detailed design documents that will enable implementation of algorithms by other teams specializing in either RTL design or DSP firmware coding.
- Optimize and fine-tune the system for spec compliance on silicon in an RF lab environment.

This role is for an analog layout IP lead who will enable us to produce fully functional first silicon IP designs. The responsibilities include all phases of silicon development from definition to high quality production.

Senior Layout Leads are responsible for delivering Analog Mixed-Signal IP in an SOC flow. They collaborate with teams of highly skilled individuals to develop the next generation of world-leading SOCs.
As a member of the AMS layout team you will be responsible to deliver Physical Design Verification clean layout, this includes the following:
Crafting complex layout for mixed signal, and analog circuits in deep SubMicron CMOS technologies.
Reviewing and analyzing floor-plans and complex circuits with circuit designers.
Running complete set of design verification tools available on AMS blocks.
Working with the circuit design team to plan/schedule work and negotiate any necessary layout trade-offs as needed.
Interpreting LVS, DRC and ERC reports to find the fastest way to complete layout.
Exceeding engineering specifications and expectations by working closely with the circuit design team.
Utilizing advanced CAD tools and mask design knowledge to deliver correct and robust layout that meet stringent matching performance, area and power requirements.

we are looking for a Senior Hardware Architect for Mobile broadband.
As a senior architect you will be a leader, someone who brings into the company new ideas and helps drive next generation wireless products
Responsibilities:
Be a leader in the Mobile Broadband team, architecting state-of-the-art modems for next generation cellular solutions. Investigate, invent, develop, innovate wireless modem components. Drive the implementation phase with the VLSI, Software and Algorithm teams.

The Storage Technologies Quality Engineering team within our CoreOS organization is looking for a results-oriented leader with strong technical and interpersonal skills to lead a team of Quality Engineers with a focus on our Software Updates validation. The person in this role will work closely with Engineering, other QA, and cross-functional managers on delivering the highest quality experience for all our products!
As a member of our dynamic group, you will have the unique opportunity to be part of validating our Software Updates components. You will be responsible for ensuring features and performance are maintained at the highest standard.

You will be managing a team of Software Development Engineers in Test, focusing on white box testing for all our Platforms. You will drive the testing, data gathering, and project reporting for your team. You will coordinate testing with other teams, review test plans and related documentation, monitor progress, and provide sign-offs on all presubmission and release milestones. You will process data from multiple sources, draw meaningful conclusions, and present valuable recommendations to leadership. You will also be expected to contribute as an individual contributor!

Responsibilities:
Manage a team of Development Engineers in Test.
Develop, modify, automate complete test strategies, plans, and programs
Coordinate testing between multiple sites.
Drive quality initiatives for areas of responsibility.
Actively participate in testing the work you're doing.

we are looking for a Senior VLSI Design Engineer.
As a Senior VLSI Designer, youll lead the full design flow of advanced DSP cores and accelerator- from architecture to timing closure. This hands-on role is key to developing the IPs behind the next-generation products, with strong cross-functional collaboration and technical ownership.
Responsibilities:
As a Senior VLSI Designer, you will be responsible for the end-to-end design and implementation of advanced digital IPs, including DSP cores and hardware accelerators. You will work across the full design flow- from architecture definition and micro-architecture design, through RTL development and verification, to synthesis, timing closure, and static timing analysis (STA). Your work will directly contribute to the silicon success of next-generation products across various domains.

we are looking for a Software Simulator Developer.
In this role, you will learn and deeply understand the AI fundamentals and create tools that simulate AI neural network processor implementation.
In addition, you will perform in-depth analysis and optimization to the simulator, to ensure simulator performance and accuracy for various processors architectures.
The project is using C/C++ OOP as main development language as well as python for AI neural network
Development platforms are Linux and Windows based.
Responsibilities:
Taking part of innovative, agile, top-notch Software organization, designing Neural Network Processor (NPU) simulator in close collaboration with the architecture, algorithms, system and hardware teams.
Design and develop simulation software solutions allowing customers to run most advanced AI networks efficiently on NPU software simulation.

Required FinOps Engineer
Job Description
As a FinOps Engineer, you'll be responsible for managing and optimizing the financial aspects of our cloud computing operations, including monitoring and controlling AI-related costs. In this role, you will work collaboratively as part of a team, demonstrate initiative, think creatively, and drive innovative solutions. You'll work closely with the CFO and VP of R&D to ensure cost efficiency, budget adherence, and financial transparency across our cloud services.
In your day-to-day, you will:
Work directly with different external hosting providers to manage hosting costs
Manage and monitor cost visibility for multi-data center architecture in a large-scale, multi-cloud environment
Work with financial teams on production-related budgets, forecasts, and expense reports
Create financial models to calculate TCO of new projects
Create financial and usage dashboards, as well as frameworks for efficiency & costs
Partner with the development, support and devops teams to encourage financial responsibility
Stay updated on industry trends and best practices in cloud cost optimization and FinOps methodologies.