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In this role you will develop system level software, targeting chip architecture, functional correctness and performance, running on various platforms and validating chip functionality.

In this highly-visible role you will assume responsibility over a full range of DFT in an extremely challenging project, leading a talented team of engineers, working closely with frontend and backend teams. You will participate in architecture and design reviews, create design solutions for testability, debug ability, reliability and yield improvement. You will provide design constraints for implementation and sign-off. You will build work plans, drive and track their execution. You will be closely involved in silicon bring-up, reliability testing and advanced physical failure analysis activities, and will be responsible for getting a high-quality product out into AWS fleet for millions of our customers quickly. Come and join us as we work hard, have fun, and make history.

Required PHY Post Silicon Validation Engineer
Job Description
What You'll Do
Youll be joining the post silicon validation team in PHY system group at Silicon One group as part of the silicon development.
Our team deals with PHY and system aspects of the SerDes communication IP: PHY FW, calibrations, system definitions and operations and post-silicon validation including developing the automation infrastructure and tools.
We use latest silicon technologies and processes to build the largest scale and most complex devices at the edge of feasibility.
Who You'll Work With
You'll be part of our Group driving our game changing next generation network devices - Silicon One. Our unique team works in a startup atmosphere inside a stable and leading corporation. The position includes hands on work in our lab in Caesarea and Netanya.
Our design center is unique - hosting all silicon HW and SW development disciplines inside one site.
We are transforming the industry and building a new internet for the 5G era, providing a unified, programmable silicon architecture that is the foundation of all our future routing products.
Our devices are designed to be universally adaptable across service providers and web-scale markets, designed for fixed and modular platforms. Our devices deliver high speed without sacrificing programmability, buffering, power efficiency, scale or feature flexibility.
Silicon One is a revolutionary, ground-breaking technology for our customers and end users for decades to come! The Internet now has a new faster, better, safer engine!

We are seeking talented, creative and disciplined engineers to join the best-in-class team that plays a significant part in the development of new silicon for our eco-systems by engaging in a dynamic, highly collaborative environment. As a Wireless MAC System Architect, you will be a core member of our highly innovative and visible Wireless System-on-Chip (SoC) design team that defines modem architectures, develops MAC-layer algorithms, and invents embedded DSP algorithms for chips enabling exciting new wireless applications. You will be responsible for developing state-of-the-art wireless SoC products that are enjoyed by millions of our customers. Application areas include ultra-wideband sensing and specialized wireless audio; products enabled or improved by our teams SoCs include specialized audio headsets (such as AirPods), watches and iPhones.

In this role you will be responsible for the architecture of the Connectivity IP with focus on the MAC sub-system: - Define, document and Spec Connectivity MAC architecture and performance requirements.
- Analyze & simulate the performance of the Connectivity IP in real-life use-cases, achieving benchmarking performances in several metrics, including Throughput, Robustness, Co-existence with other Wireless IPs and more.
- Working closely with other architects (PHY, Power Management, FW and SW) to introduce best in class Connectivity IP solution.
- Develop innovative system architectures and protocols to deliver best-in-class performance for the MAC subsystem of custom wireless silicon solutions.
- Introduce cross-domain features where opportunities exist for innovation to achieve enhanced performance.
- Produce MAC architecture, specifications and corresponding performance/reference modeling in support of digital HW and FW design and verification efforts.
- Develop and maintain a MAC systems infrastructure applying the best methodologies for system-level simulation, pre-silicon prototyping (including emulation and FPGA prototyping), FW QA, regression and MTBF testing, and system verification to ensure first-time design success.
- Support the delivery of new wireless technologies to the Product Systems teams.

Required PHY System
Job Description
Join the PHY system team at Silicon One, a pivotal part of our silicon development. Our team focuses on the PHY and system aspects of our devices, including PHY firmware, calibrations, system definitions, operations, and post-silicon validation.
Key responsibilities include:
Working with the latest silicon technologies and processes to build large-scale, complex devices at the forefront of feasibility.
Contributing to the development of PHY firmware and system calibrations.
Participating in system definitions, operations, and post-silicon validation activities.
What Youll Do:
Youll be part of the group driving next-generation network devices-Silicon One-within a startup-like atmosphere inside a well-established, leading corporation.
Our unique design center integrates all silicon hardware and software development disciplines under one roof. We are revolutionizing the industry by building a new internet for the 5G era, with a unified, programmable silicon architecture that will underpin our future routing products. Our devices are designed for adaptability across service providers and web-scale markets, delivering high speed without compromising programmability, buffering, power efficiency, scale, or feature flexibility.

Required Senior Electrical Post Silicon Validation- Silicon One
Job Description
Meet the Team
We are a dynamic group of engineers dedicated to pushing the boundaries of technology. Our mission is to validate and drive the performance of Silicon One products, ensuring they meet the highest standards of quality and reliability.
Operating at the forefront of technology, we work with latest, high-speed, and power-hungry devices. Our small, but highly influential team thrives in this challenging environment, applying our expertise to impact the future of networking technology. With a commitment to excellence and a passion transformative technology, we are shaping the future of high-performance Networking and delivering unparalleled value in every project we undertake. Join us, and be a part of a team where professionalism meets impact!
Your Impact
Drive the resolution of complex silicon performance and characterization issues through deep, multi-functional collaboration with architecture, design, and software teams. Leverage these technical insights to provide critical feedback that directly influences the design, debuggability, and architectural specifications of future silicon components
Key Responsibilities:
Lead the Electrical Post Silicon Validation efforts for Silicon One products, focusing on high-speed and power-intensive devices. Collaborate with multi-functional teams to drive the silicon validation process, from architecture through to physical design and DFT. Analyze and interpret characterization data to guide design improvements and ensure product excellence. Develop and execute test plans to validate silicon performance and reliability against stringent specifications. Troubleshoot and resolve issues related to silicon performance and characterization.
Why Join Us:
Be part of team at the forefront of silicon technology, working on the most advanced products in the market. Work closely with some of the best engineers in the industry, driving innovation and excellence in silicon characterization. We are a fast growing team that values talent and provides ample opportunities for professional development and career advancement.

Develop and maintain internal EDA tools and frameworks for RTL assembly and connectivity checking.
Implement efficient algorithms for hierarchical RTL construction, module binding, and interface consistency across complex SoCs.
Build intelligent connectivity, visualization, and debug utilities.
Collaborate with front-end design, DFT, and integration teams to align methodologies and define tool requirements.
Drive automation and performance improvements, including runtime optimization and scalability across large designs.
Support adoption, documentation, and user training for internal design teams.

Required PHY Firmware Technical Leader
Meet the Team
Join the Silicon One PHY System team, part of our core silicon development group.
Our team is responsible for PHY and system-level aspects of some of the most advanced networking devices in the industry, including PHY firmware, calibrations, system definitions, operations, and post-silicon validation.
We work with the latest silicon technologies and processes to build large-scale, highly complex devices at the edge of feasibility. Youll be part of a unique design center that hosts all silicon HW and SW disciplines under one roof, operating in a startup-like environment within a stable, world-leading company.
We are transforming the industry with a unified, programmable silicon architecture that powers our future routing portfolio and helps shape the Internet for decades to come.
Your Impact:
Develop PHY firmware and system-level features for advanced networking ASICs
Participate in post-silicon validation, including lab bring-up, debugging, and performance analysis
Collaborate closely with PHY, system, firmware, and silicon design teams
Contribute to defining system operation modes and end-to-end device behavior
Help drive the development of next-generation, high-scale networking solutions using cutting-edge silicon technologies
Who Youll Work With:
The Silicon One group, the center of our ASIC design efforts
Cross-functional teams including silicon design, firmware, and system
Global teams working together to deliver game-changing networking devices

we are seeking for an Systems Analyst This role requires leading and developing system specifications, interfaces between systems, reports, and data cleansing processes, as well as working with business processes in the fields of smart metering and consumer systems. Full-time position, Sunday-Thursday, based in Gan Sorek.

This role has been designed as Hybrid with an expectation that you will work on average 2 days per week from our office.

Roles and Responsibilities:
Design, develop, and enhance I/O subsystems, virtualization, kernel programming, and memory management for cutting-edge system software products.
Drive performance optimization, and efficient memory management.
Perform in-depth debugging, triaging, and resolution of user and kernel-level, performance profiling, and memory-related issues.
Develop innovative solutions, addressing challenges in virtualization, multithreading, and hardware-software interaction.
Explore and implement new methodologies fostering continuous improvement and innovation.
Proactively identify bottlenecks in system design, and recommend and implement robust, scalable solutions.
Stay updated on evolving trends in kernel development, design, and virtualization technologies to bring innovative practices to the team.
Troubleshoot and optimize complex I/O and kernel features to enhance performance, scalability, and reliability.
Collaborate with cross-functional teams to align on design goals and ensure seamless integration with the system architecture.
Exhibit flexibility in taking on new or related tasks, showcasing adaptability and a proactive, problem-solving mindset.
Provide technical leadership in architecture design, problem-solving, and decision-making across complex technical domains.
Lead technical discussions, design reviews, and decisions on critical system challenges, driving the adoption of innovative solutions and best practices.

As an Associate Application Engineer, you will be involved in a structured Associate Application Engineer Training Program. This is a fast-track paid training program that challenges you to develop the expertise needed to tackle difficult technical problems.
Associate Application Engineers are members of a team of highly motivated individuals working with customers crafting the most sophisticated hardware and software systems in the world and whose applications span the electronics industry. This training program will give you outstanding insight into our technical marketing, product support, and sales organizations. Upon successful completion of this 12-month training program, you will be eligible to advance into one of these organizations.
The job location is in Israel in our Raanana office.

we're seeking a visionary Physical Design Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the backend execution and methodologies for chips that power the world's largest AI clusters.

As a Physical Design Engineer, you will be a key architect of our silicon's physical reality. You won't just execute a flow-you will help establish our local execution culture and technical standards, owning the transformation of complex logic into high-performance silicon. You will drive the physical implementation journey from synthesis through signoff, ensuring our connectivity solutions meet the extreme performance, power, and area targets required for next-generation AI infrastructure. If you thrive on solving complex challenges in deep-submicron processes and want to shape the backend methodology for AI infrastructure connectivity, this is your opportunity.

Key Responsibilities

Physical Implementation & Execution

Be part of the founding Backend team in Israel, playing a critical role in establishing local execution culture and technical standards
Take full responsibility for physical implementation journey including Synthesis, Floorplanning, Place & Route, and Clock-Tree Synthesis (CTS)
Own macro-level implementation with deep hands-on experience in floorplanning and complex routing
Signoff & Design Integrity

Drive final stages of design integrity, owning Timing signoff (STA), Physical Verification (DRC/LVS), and Reliability analysis (EMIR)
Ensure first-pass silicon success through rigorous signoff flows and analysis
Apply Logic Equivalence Checking (LEC) and other verification techniques to guarantee design correctness
Methodology Development & Cross-Functional Collaboration

Participate in defining and refining Backend methodologies with autonomy to improve workflows and tool automation
Work closely with Architecture, Design, and DFT teams to navigate challenges of advanced process nodes and high-speed connectivity
Leverage scripting and automation to make engineering environment faster and more robust

we're seeking a visionary Senior DFT Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, ensuring the reliability and testability of chips that power the world's largest AI clusters.

As a Senior DFT Engineer, you will be at the intersection of architecture, design, and production. You won't just run tools-you will be a foundational member of the team responsible for the entire lifecycle of our silicon's reliability. From defining initial DFT architecture to supporting post-silicon bring-up, your work ensures that the backbone of AI infrastructure connectivity is flawless and scalable. If you thrive on solving complex challenges in deep-submicron processes and want to establish world-class DFT methodologies, this is your opportunity.

Key Responsibilities

DFT Architecture & Strategy

Own the DFT journey from high-level architecture definition and RTL design to backend implementation and post-production support
Develop comprehensive Design-for-Testability (DFT) strategies for next-generation connectivity platforms, ensuring chips meet the highest quality standards
Define DFT architectures including JTAG/iJTAG, MBIST, Scan, and ATPG methodologies
Test Pattern Development & Optimization

Generate and optimize high-quality test and debug patterns for production
Perform Static Timing Analysis (STA) for DFT modes and conduct gate-level simulations to ensure robust performance
Drive test coverage and quality metrics to meet stringent manufacturing requirements
Cross-Functional Collaboration & Methodology Innovation

Act as a multidisciplinary bridge, collaborating closely with Architecture, Verification, and Backend teams to ensure seamless integration and optimal QoR
Participate in developing and maintaining cutting-edge DFT implementation flows
Automate and improve methodologies using advanced scripting and tools

we're seeking a talented Senior Emulation Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful ownership in a new site, implementing the emulation strategy for chips that power the world's largest AI clusters.

As an Senior Emulation Engineer, you will be a core technical driver of our Israel R&D center, working at the intersection of hardware and software to ensure our silicon meets extreme quality and performance targets. You will execute end-to-end emulation flows, bridge the gap between RTL and functional validation, and partner with cross-functional teams to enable seamless hardware-software integration. If you thrive on solving complex technical challenges and want to play a key role in validating cutting-edge AI infrastructure connectivity solutions, this is your opportunity.

Key Responsibilities

Emulation Flow Execution & Implementation

Execute end-to-end emulation flow from high-level model generation and RTL synthesis to complex system-level testing and silicon-accurate debugging
Work directly with next-generation emulation platforms (Zebu, Palladium, or Veloce) to implement cutting-edge methodologies
Maintain and evolve emulation flows to reduce compile times and increase execution speed, directly impacting time-to-market
System-Level Debug & Validation

Drive initial model bring-up process in high-stakes environment, identifying and resolving complex bugs
Ensure rapid cycles from RTL to functional stability through systematic debug approaches
Own technical blocks and drive them to completion independently
Cross-Functional Collaboration

Partner with Firmware, Software, and Validation teams to debug complex system-level scenarios
Ensure seamless hardware-software integration for AI infrastructure connectivity
Collaborate with Design and Verification teams to optimize emulation strategies

we're seeking a highly skilled Chip Top Physical Design Engineer focusing on implementation to join our local engineering powerhouse from the ground up.
If you thrive on solving complex, unnamed challenges in deep-submicron processes, your place is with us.

As a Physical Design Engineer, you will be a key hands-on member of our PD Team in the Israel R&D center. You will execute the physical design of the SoC Top level for chips that drive the worlds largest AI clusters. You will be deeply involved in all PD disciplines of the chip, driving the tape-out (T.O.) GDS to meet strict signoff criteria (Timing, LVS, EMIR, DRC, PV, etc.), ensuring our silicon meets the extreme performance, power, and area (PPA) targets required for AI scale.

Key Responsibilities


Execute SoC Top-level physical design and actively drive full-chip convergence
Perform Top-Level physical implementation, including floor-planning, Place & Route (P&R), Clock Tree Synthesis (CTS), Power/Clock distribution, Power Integrity, and Timing/Physical signoff
Work closely with the Architecture, Design, DFT, and Product teams to achieve optimal Power, Performance, and Area (PPA). This involves participating in feasibility studies for new architectures and optimizing runs to ensure the best Quality of Results (QoR)
Resolve complex signal integrity, thermal, and power challenges inherent in high-speed connectivity silicon
Collaborate closely with the Package team on Bump-map-to-Ballout design, taking all signal integrity aspects into consideration