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Space Systems Development Manager We are seeking an experienced Space Systems Development Manager to lead the development of advanced space systems from concept through delivery.
Responsibilities:
Lead multidisciplinary teams across systems, software, and hardware
Manage end-to-end development, including requirements, design, integration, and validation
Drive system architecture and ensure successful delivery.

We are currently seeking a Senior FPGA Engineer to join one of our trading teams. While our company has been leveraging FPGA technology for a number of years, you will have the opportunity to build an FPGA application from scratch for an existing team. Were seeking a candidate that has a strong understanding of software and hardware interaction. This person will participate in the full development lifecycle, including system and block level testing, of low latency high throughput FPGA design.
Responsibilities:
Architect and implement new FPGA applications (synthesis, place & route, static timing analysis, documentation) from the ground up
Research and evaluate a variety of cutting-edge FPGA hardware and technologies
Propose creative solutions to overcome FPGA/hardware limitations
Liaise directly with software and other design teams
Conduct lab debugging and characterization of new hardware.

We are looking for a hands-on ETH SerDes Validation Engineer to lead and execute 112G and next-generation 224G SerDes validation activities.
The role involves deep lab work with Keysight test equipment, automation development, and direct execution of compliance and characterization tests according to industry standards.
This position is ideal for an engineer who combines strong signal-integrity fundamentals, standards expertise, and automation-driven validation in high-speed silicon and system environments.
Key Responsibilities
Perform end-to-end validation of 112G / 224G SerDes PHYs at silicon, package, and system levels
Execute compliance, characterization, and stress tests for high-speed serial links
Operate and configure Keysight high-speed test equipment, including:
BERTs, oscilloscopes, AWGs, jitter sources, channel emulators (variable ISI)
Develop and maintain automation frameworks for SerDes validation:
Test setup control
Data collection
Result analysis and reporting
Python
Shell scripts under Ubuntu
SQL skills for data analysis
Execute and analyze:
Eye diagrams, jitter (RJ/DJ/TJ), BER, bathtub curves
CTLE/DFE behavior
TX FIR optimization
Channel loss and margin analysis
Debug signal-integrity issues across:
Silicon
Package
PCB
Connectors and cables
Work according to industry standards, including:
IEEE (112G / 224G PAM4)
Ethernet (802.3ck / 802.3db and beyond)
Collaborate closely with:
Design teams (SerDes / PHY)
SI/PI engineers
System and board design teams
Document test methodologies, results, and recommendations clearly.

We are looking for a System Engineer Lead to lead our next generation system development.
In this role, the Project Lead will technically lead a complex multidisciplinary electro-optical system architecture. He will define and manage the required performance analysis, technical solutions, implementation methods, and field deployment to the customer's satisfaction.
Responsibilities
What you will be doing:
Technical:
Design the system architecture/high-level design and technical requirements.
Serve as the system go-to person for all technical matters; a technical expert knowledgeable in system operation, performance, and troubleshooting. Act as the technical POC for system escalations and customer support.
Project Management:
Plan, monitor, and lead the project to ensure product delivery within required specifications, on time, and within the allocated budget (Gates, PMR).
Maintain a project risk management and mitigation plan.
Lead the development activities and technical reviews throughout the PLC (SRR, PDR, CDR, FDR) and other technical design reviews.
Assign project tasks, follow up, and align with development groups, service, and production.
Lead all aspects of the beta tool delivery.
Act as the key contact for inbound topics (matrix interface) and outbound topics with MKT.
Team:
Develop and grow team ownership and technical capabilities.
Provide technical guidance for System/Product engineers.

The Production team is looking for a Production Integration Engineer to join the integrated metrology line and work on state of the art tools in the semiconductor industry.
Your role will be to manufacture the company products while maintaining highest quality and on-time delivery.
As part of your job you will interact and work with the Engineering, R&D and QA departments to solve complicated on tool problems and test new tools and features as part of the transfer to production process.
Responsibilities
What will you be doing:
Lead tool manufacturing process from start to end (1-2 weeks project).
Integration of multidisciplinary systems (optical, electronic, pneumatic, computing, and mechanical) according to predefined procedures.
Ability to solve complex system challenges, constantly learning and striving to independence.
Working with engineering and R&D to address systems/production process challenges.
Addressing quality issues and repair recommendations for suppliers by nonconformance report.
Working in an organized way using digital procedures and flow management system.
Always striving to reduce cycle time and improve working process.
Helping and consulting team members to overcome challenges on their tools.

As a Wireless Design Verification Engineer, you will be part of a team that is responsible for pre-silicon RTL verification of communication subsystems, SoC sub-systems and chip-level functionality. The activity may focus on block level, sub-system level or chip level, including end-to-end simulations of the entire data/control path. You will interact with DV methodologists, designers and communication systems engineers to develop reusable testbench and verification environment deploying the latest methodology with metric driven verification.
Description
- Own critical block and sub-system verification of wireless SoC projects
- Architect and develop testbenches and environments, by using state-of-the-art verification methodologies
- Define verification plan, create, simulate and debug test scenarios
- Drive regression and coverage analysis to ensure high quality DV
- Collaborate with design and systems engineering teams to review requirements, specifications and architecture, extract features and define DV attribute

Required Radar Systems Engineer.

The Junior / Trainee Instrumentation and Electrical Technician supports the installation, calibration, maintenance, and troubleshooting of instrumentation, control and electrical systems used in oil and gas operations. This role is designed for entry-level candidates and focuses on developing technical skills while working under close supervision of senior technicians, ensuring safe and reliable plant operations.

Ashdod, Southern District

Demonstrates ability to monitor and operate plant equipment and conduct routine duties and non-routine Operations activities.

Maintain a clean and organized work environment to identify hazards.

Toolbox talk and last-minute risk assessment using COW processes for a specific activity.

Demonstrates basic technical competencies and capabilities in upstream/ midstream/ downstream and manufacturing plant operations, including pipeline and hydrocarbon behavior

Demonstrates ability to troubleshoot and solve basic operational problems by teaming and collaborating with cross-functional teams

Supports and properly responds to unplanned events and their impact on equipment and operations.

Comply with the Companys safety standards, policies, and regulatory requirements

Identify and describe basic step-by-step maintenance requirements in Gas and chemical streams

Report and identify the source of surface staining on tanks and equipment.

Maintain, record, and inventory production supplies

It has basic ability to read/interpret/field as-built P&IDs, SAFE Charts, Cause & Effects.

Basic abilities to analyze trends of efficiency degradation on production equipment

Performs basic analysis of Process Safety Management (PSM)

Utilization of computerized systems, including SAP, D2 (document control), Enablon (E-PTW), and Bluebeam Revu.

Execute and understand MOC and RIK processes

Execute level 1 and level 2 Hazard analysis in general work, breaking containment, isolation of hazardous energy, bypass critical protection, and stop work authority to ensure safe operation.

This position is responsible for interpreting Control Philosophies, Cause & Effects, P&IDs and developing, testing, documenting, and maintaining Rockwell ControlLogix PLC & FactoryTalk HMI based systems and Archestra System Platform object-based programs, templates, processes, and tools to manage and sustain programming code for offshore and high-pressure gas production facilities. Supports project activities including facility design, construction, commissioning, troubleshooting, managing, and maintaining SCADA, DCS, SIS, HMIs, PLCs, PCN Servers & Applications and Communication systems reliability and availability. Maintains SCADA data reporting systems, support Operations production reliability and optimization efforts and support PCN Information Risk Management (IRM) compliance. Train and mentor Operations and Maintenance personnel.

At High Sec Labs (HSL), a global leader in cybersecurity and secure connectivity solutions, we are looking for a talented Electronics Engineer to join our advanced development team. About the Role:
As part of our hardware group, you will take an active role in developing cutting-edge electronic products in the communication and cybersecurity domains. The role involves end-to-end board design, bring-up of new products, and integration of complex systems combining RF circuits, analog components, processors, and FPGAs.
Key Responsibilities: Design, bring-up, and validation of electronic boards and systems. Integration of RF, analog, digital, and FPGA-based circuits. Debugging, troubleshooting, and improving existing products. Close collaboration with multidisciplinary teams, including software and system engineers. Supporting the full product lifecycle from concept to production.

As a Design Verification Manager for the IP Group, you will lead a focused team responsible for the quality and reliability of our critical IP blocks. You will steer the IP verification roadmap, oversee the development of complex testbenches, and ensure our next-generation AI silicon meets the highest standards. Leading a team of talented engineers, you will tackle challenges at the unit and sub-system levels, playing a pivotal role in delivering high-performance hardware for the worlds largest AI clusters.

Key Responsibilities



Lead and mentor a team of design verification engineers, defining the technical roadmap and methodology for ASIC verification across unit and IP/sub-system levels
Drive the creation and execution of comprehensive design verification plans, ensuring all functional requirements are met on schedule for complex digital IPs
Oversee the architecture and maintenance of block-level verification strategies, heavily utilizing SV-UVM, alongside Formal Verification where applicable
Define functional coverage goals and quality metrics, driving the IP team toward 100% verification closure and sign-off
Partner closely with IP Design and Architecture teams to align on specifications, root-cause complex bugs, and optimize the IP development cycle

As an Expert EMIR & Power Integrity Lead, you will be a core technical contributor ensuring the power robustness and long-term reliability of our high-performance connectivity silicon. You will own from block level to full-chip the Electro-Migration and IR Drop (EMIR) methodology, analysis, and sign-off, working at the intersection of Physical Design, Analog/Mixed-Signal design, and Package Engineering.

You will be responsible for defining power grid architectures and validating that products meet aggressive voltage drop and reliability targets in advanced FinFET process nodes. Your work will directly impact the performance and yield of chips operating in the worlds most demanding AI and cloud environments.

Key Responsibilities

Lead static and dynamic IR drop analysis, signal/power electromigration (EM) verification, and self-heat analysis from block level to full-chip sign-off
Define and implement robust EMIR flows and methodologies using industry-standard tools (Ansys RedHawk-SC, Cadence Voltus, or equivalent)
Collaborate with Physical Design teams to define optimal power grid structures, via pillars, and strap distributions to minimize voltage drop while maximizing routing resources
Work closely with Analog/SerDes designers to analyze current profiles and ensure robust power delivery to sensitive high-speed IP blocks
Partner with Package Design engineers to perform Chip-Package-System (CPS) co-analysis, optimizing bump patterns and package routing for superior Power Integrity
Drive root-cause analysis for voltage drop violations and EM risks; propose and implement layout fixes alongside the PD team
Verify current density rules for ESD protection networks and ensure compliance with foundry reliability constraints
Support silicon bring-up by correlating simulation results with actual silicon measurements and yield data

we're seeking a visionary Expert IC Package Design Lead to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, leading the physical implementation strategy for chips that power the world's largest AI clusters.

As an Expert IC Package Design Lead, you will be a core technical contributor in the development of advanced IC packaging solutions for high-performance connectivity silicon.
You will own package flow, architecture, design, and qualification from concept through production, working closely with silicon, signal integrity, power integrity, mechanical, manufacturing, and external OSAT partners.You will be responsible for defining package technologies that meet aggressive electrical, thermal, mechanical, and cost targets, enabling products to operate reliably in the worlds most demanding AI and cloud environments.

Key Responsibilities

Own end-to-end IC package design, from early architecture and feasibility through detailed design, qualification, and high-volume manufacturing
Define package architecture and technology selection (organic substrates, advanced laminate, interposers, multi-die/chiplet packaging, CoWoS - 2.5D/3D integration)
Lead signal integrity (SI), power integrity (PI), and thermal considerations at the package level for high-speed, high-power devices
Drive package layout, substrate routing, bump/ball maps, stack-ups, materials selection, and mechanical constraints
Collaborate closely with silicon design, SerDes, system, SI/PI, and reliability teams to optimize overall product performance
Interface with OSATs, substrate vendors, and manufacturing partners to ensure design-for-manufacturability (DFM), yield, and cost targets
Lead package-related risk assessment, failure analysis, and corrective actions during bring-up and production ramp
Support NPI, qualification, and product sustainment activities, including vendor audits and technical reviews