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In this role, you will provide technical support to customers, troubleshoot networking and communication solutions, and collaborate with Engineering and Product Management to resolve technical issues efficiently.

You will also deliver professional services and support customers both remotely and on-site.

This is a full-time position with the option of working from home one day a week.

Location: Tel Aviv office Ramat-Hachayal.

Key Responsibilities
Serve as the primary technical contact for assigned customer support cases via phone, email, and web.
Troubleshoot and resolve network configuration issues, equipment faults, and product-related problems.
Analyse customer network environments to identify root causes and recommend effective solutions.
Collaborate with Engineering, Product Management, and Tier-3 Support teams to resolve complex technical issues.
Deliver Professional Services, including product implementation, configuration, technical trainings, technical consulting, etc
Provide on-site installation, troubleshooting, and technical support when required.
Maintain high levels of customer satisfaction by delivering timely, professional, and effective technical support.

We are looking for a motivated and detail-oriented Safety Laboratory Technician to join our Hardware Department lab team at our Tel- Aviv office.

The successful candidate will perform safety testing of company products in accordance with international safety standards. Comprehensive professional training will be provided as part of the role.

Key Responsibilities
Perform safety testing of company products in accordance with international safety standards.
Operate laboratory test and measurement equipment.
Set up, execute, and document safety test procedures.
Prepare clear and accurate test reports.
Maintain laboratory equipment and ensure compliance with laboratory procedures.
Work closely with engineering and regulatory teams to support product certification activities.

We are looking for a versatile Senior Software R&D Engineer and a dedicated team member to join our multidisciplinary group. This role places a heavy emphasis on hardware bring-up, low-level software development, and collaborative engineering. You will be a core player in a tight-knit team, moving seamlessly between different phases of system creation-from architecting board support packages (BSPs) and troubleshooting new hardware boards to designing high-performance application features.

Location: Ramat Hachayal, Tel Aviv. Hybrid option once a week.



Responsibilities:
Active Team Member: Collaborate daily within a diverse R&D team. Brainstorm solutions, conduct peer code reviews, and share knowledge to elevate the teams capabilities.
Hardware Bring-up & BSP: Lead the software-side bring-up of next-generation hardware. Design, develop, and debug Board Support Packages (BSPs) to seamlessly bridge the hardware-software boundary.
HW/SW Integration: Partner closely with hardware engineers to diagnose system-level bottlenecks, read schematics, and ensure optimal hardware performance.
Real-Time Feature Implementation: Design and develop high-performance software features and real-time application layers for our flagship product.
Product Implementation Design: Translate complex product requirements into scalable, highly reliable software designs and system architecture.

Key job responsibilities
* Daily involvement in all aspects of physical design chip development (RTL2GDS), including floorplanning, synthesis, clock tree synthesis, place and route, static timing analysis, power and noise analysis, physical verification testing, and equivalence checks.
* Being actively engaged in design-backend convergence aspects and defining timing constraints.
* Taking full end-to-end responsibility for the physical design of macro and cluster-level blocks, according to specifications, under challenging constraints, with focus on optimizing power, area, and performance.
* Participation in the development of design flows, using a variety of EDA tools and vendors such as Synopsys and Cadence.
* Engaged in defining implementation and signoff methodologies.

We are looking for a talented Development Engineer to join our team and take part in building innovative software solutions in a dynamic and challenging environment.

Location: Ramat Hachayal, Tel Aviv. Hybrid option once a week.

we are looking for a Logic Design Engineer.
Your Impact:
Write and review micro-architecture specifications
Implement RTL (Verilog/SystemVerilog) to meet timing, performance, and power requirements
Contribute to full chip integration, timing methodology, and analysis
Collaborate with verification engineers to resolve bugs and achieve coverage closure
Work with the physical design team to close timing and PnR issues
Support design methodology evolution and best practices
Perform debug, root-cause analysis, and post-silicon validation in the lab

Key job responsibilities
* Design and implement advanced Design-for-Test (DFT) architectures for complex semiconductor platforms.
* Develop high-quality test and debug patterns ensuring robust performance.
* Conduct comprehensive static timing analysis across multiple DFT modes.
* Verify intricate DFT logic and components with precision and creativity.
* Support silicon bring-up and device diagnostic processes.

Your day will be filled with complex problem-solving and collaborative innovation. You'll work alongside world-class DFT engineers in a dynamic environment, developing semiconductor technologies that support global cloud infrastructure. Our team thrives on creativity, technical excellence, and continuous learning.

We are looking for talented Software Development Engineers to join our teams in Tel Aviv or Haifa and work on low-level software development. You will be building the foundational software layers that sit closest to the hardware - enabling high performance, reliability, and efficiency for AWS services at an unprecedented scale.

This is an opportunity to work in a deeply technical environment where your code runs on custom-designed silicon, directly impacting the performance and cost of cloud infrastructure used by millions of customers worldwide.

Design, develop, and optimize low-level software including device drivers, firmware, and hardware abstraction layers.

Collaborate closely with hardware design teams to define hardware-software interfaces and bring-up new silicon.

Write performance-critical systems software in C/C++ that operates under strict latency and resource constraints.

Debug complex hardware-software interactions.

Contribute to system architecture decisions and define software design patterns for next-gen chip features.

Develop and maintain automated test frameworks to validate functionality and performance at scale.

Participate in code reviews and drive engineering best practices within the team.

Lead verification for advanced ASIC/FPGA designs in a top-tier R&D team developing high-performance network interface solutions and customer-focused hardware.

Location: Tel Aviv office or our Beer Sheva office, which is located next to the train station



Responsibilities:
Drive verification of complex, high-speed ASIC/FPGA designs
Define and implement advanced verification methodologies
Collaborate with architecture, software, and validation teams
Mentor engineers and promote technical excellence
Work with technologies like high-speed interfaces, network processors, and SoCs

We're looking for curious minds who think big and want to define tomorrow's technology. At Amazon, you'll grow into the high-impact engineer you know you can be, supported by a culture of learning and mentorship. Every day brings exciting new challenges and opportunities for personal growth.

Key job responsibilities
- Collaborate and communicate effectively with experienced cross-disciplinary Amazonians to design, build, and operate innovative products and services that delight our customers, while participating in technical discussions to drive solutions forward.
- Design and develop scalable solutions using cloud-native architectures and microservices in a large distributed computing environment.
- Participate in code reviews and contribute to technical documentation.
- Build and maintain resilient distributed systems that are scalable, fault-tolerant, and cost-effective.
- Leverage and contribute to the development of GenAI and AI-powered tools to enhance development productivity while staying current with emerging technologies.
- Write clean, maintainable code following best practices and design patterns.
- Work in an agile environment practicing CI/CD principles while participating in operational responsibilities including on-call duties.
- Demonstrate operational excellence through monitoring, troubleshooting, and resolving production issues.

we are looking for a Senior Physical Design Engineer.
Your Impact:
You'll be part of the team, which is at the heart of software and ASIC design efforts.
You'll handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.

Required Software Engineer, ML (Technical Leadership)
The financial risk management (FRM) machine learning principal will be the most senior machine learning engineer and strategist for financial risk. The principal will enable the risk organization to deliver significant lift over current long range objectives for friction and leakage through the generation of new Machine Learning opportunities for the organization and support of successful delivery of the risk management ML architecture. This person will partner closely with the FRM engineering leader (Director level) and be part of our risk management leadership circle.
Software Engineer, ML (Technical Leadership) Responsibilities
Address core business and technical machine learning opportunities: elevate the existing portfolio of machine learning solutions to be state-of-the-art for minimizing our financial losses (due to leakage, good revenues loss and friction). Following are a few examples of technical and business problems we aim to address. - Provide a solution for optimizing the risk machine learning model ensemble (covering the entire end-to-end advertiser funnel including detection, decisioning, enforcement and remediation) through optimization of the current model portfolio and individual models. - Minimize the impact of the prolonged financial fraud feedback loop. - Improve models measurement and performance. - Optimize data/label strategy. - Optimize balance between specific targeted model strategy and broad umbrella model strategy to optimize for short and long term benefits
Lead Research and Introduction of Advanced Technologies: - Collaborate with Financial Integrity's senior ML Engineers to lead the research and introduction of deep learning and Large Language Model (LLM) technologies. - Remain current on industry-wide advancements in ML and introduce relevant advancements in Financial Risk Management
Collaborate on Next-Generation ML Architecture: - Work closely with financial harms principals and risk management tech leads to deliver the next-generation ML architecture for our risk management system. - Collaborate with Principal ML engineers from across the company to adopt best industry and our practices within the FRM team. - Resolve or mitigate design dilemmas, balancing business and technical trade-offs. - Identify and initiate opportunities for collaboration and impact with other organizations
Identify and Initiate New Business Opportunities: - Collaborate with our FinTech, Central Integrity and Core Ads Growth partnerships to identify and initiate new business opportunities based on third-party capabilities. - Conduct proof of concept for different opportunities and initiate integrations to enhance business performance
Grow Other Senior ML Engineers - Actively invest in the growth of other senior ML engineers through goal-driven formal and informal mentorship. Provide regular feedback to other engineers regarding their technical work.

We are looking for a junior Embedded Software Engineer, to join us in building the next generation of networking products. Youll have the opportunity to work on the technologies that power the worlds largest cloud provider, in a dynamic, open, fast-paced environment. Working for Annapurna Labs is thrilling and a constant learning experience. As an embedded SW development engineer, you will be responsible for developing features for Annapurna Labs next-generation hardware, to enable high network bandwidth and packets-per-seconds (PPS) performance, with consistently low latency. You will work to bring up a broad selection of instance types, optimized for various use cases, to suit each of our customers needs, such as varying combinations of CPU, memory, storage, and networking capabilities. As a SW development engineer, you will play a key role in shaping architecture definitions and SW system designs, and help to resolve complex customer issues. You will continuously evolve technically, while working to monitor AWS cloud health, maintain high quality standards, develop highly-optimized code, and provide exceptional customer satisfaction.

Key job responsibilities
We will be conducting a unique onboarding training program, where you will be studying the following with our technical experts and team leaders:
* Embedded systems basics.
* Annapurna technologies in EC2.
* Cloud compute development.
* Networking 101.

we are looking for a IC Package Design Engineer.
In this role, you will contribute to the development of complex ASIC package designs from early planning and exploration through implementation and tapeout. You will collaborate across package design, layout, SI/PI, and silicon teams to help deliver high‑speed, robust, and manufacturable package solutions.
You will participate in package architecture activities, design tradeoff discussions, and technical problem solving while growing your expertise in advanced packaging technologies and system-level integration. This role provides an opportunity to work on some of the most advanced networking silicon products in the industry within a highly collaborative engineering environment.
Responsibilities:
As a member of the Package Design team, you will:
Lead the package design activities including planning, floorplanning, pinout optimization, stack‑up definition, and high‑speed routing suport.
Collaborate with SI/PI, silicon floorplanning, layout, and manufacturing teams to ensure high‑quality package solutions.
Support package implementation activities and work closely with layout designers to ensure alignment between design intent and physical implementation.
Participate in technical investigations, design reviews, and tradeoff discussions involving performance, manufacturability, and schedule considerations.
Assist in developing and improving package design methodologies, flows, and best practices.
Contribute to debugging, issue resolution, and package bring‑up activities as needed.

We are excited to announce that the team is undergoing rapid growth, and we are looking for a C++ Software Developer.
Your Impact:
Craft and develop software driving the world's most complex infrastructures
Gain intimate knowledge of world-class silicon and programming models
Work with architecture and design teams to define the next generation of ASIC products being developed