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The ideal candidate will bring our collective creative vision to reality through the authoring of HTML, CSS, and JavaScript (both server and client side). The right candidate will thrive in a collaborative environment and can advocate for exceptional solutions that are in the best interest of the client.

Responsibilities:
Project Manager manage large projects including timeline, budget, scope, C level relationships/expectations. Participate in end to end implementation planning and manage day-to-day execution of project implementations. Assist with the planning, tracking, documentation, issue management and status updates for the project.
Manage end-to-end functionality as it relates to the analysis, design, build, test, and deployment of enterprise level solutions.
Create and manage project plans; monitor and review project progress and timelines; adjust schedules and plans as needed; and identify and resolve issues to ensure project success.
Adopt a standardized development lifecycle methodology for all projects.
Develop and maintain numerous project deliverables that support the solution design including discussion documents and other project artifacts.
Establish and maintain Trusted Advisor status with Project, Business and Technology stakeholders
Facilitate requirements gathering, including review sessions, and assist with the creation of project deliverables, as needed.
Hands-on application configuration/customization to meet client needs.
Manage UAT with end users including coordination and user acceptance signoff.
Collect, formulate, and disseminate best practices on project implementation, solution positioning and delivery. Provide feedback to Engagement Managers and Executive Sponsors when necessary.
Have difficult conversations regarding budget, resources and timeline and formally capture and communicate outcomes of those meetings.
Travel may be required.

We are looking for a talented Data Scientist who is a strong team player to join our Data Science team. As a Data Scientist, you will play a key role in shaping our analytics pipeline. Dive into diverse datasets, using ML algorithms, and lead end-to-end projects - starting from gathering requirements, through development, to deployment and presentation to stakeholders. Your Python expertise, along with data-driven thinking, will contribute to predictive insights and innovative solutions.
Key Responsibilities
Own end-to-end development cycle- from business understanding to development, deployment and monitoring
Develop, maintain and improve advanced AI/ML models with a wide range of tasks and diverse datasets (structured, text, images)
Interpret data using statistical techniques and leverage machine learning algorithms to drive actionable insights.
Collaborate with cross-functional teams, including engineers and product managers, to understand business challenges and design data-driven solutions.

we are looking for forward-thinking, self-motivated engineers who thrive in fast-paced environments and "crisis times." Beyond technical excellence, successful candidates are:
Intrinsically, see the importance of every detail in "elegant solutions."
Excellent interpersonal and communication skills to work across diverse functional areas.
Schedule-driven with a desire to solve challenges that have never been solved before.
Responsibilities
Micro-Architecture & RTL: Design and implement high-quality, power-efficient RTL (Verilog/SystemVerilog) from block-level to sub-system levels.
Cross-Functional Collaboration: Partner with Architecture, Algorithm, Software, and Physical Design (PD) teams to translate product requirements into GDS-ready silicon.
Front-End Flow Management: Take ownership of "correct-by-construction" design tasks, including Synthesis, Lint, CDC/RDC (Clock/Reset Domain Crossing), and STA (Static Timing Analysis).
Verification Support: Work closely with Design Verification (DV) and Formal Verification teams to define coverage requirements, develop testbenches, and debug functional/performance issues.
Post-Silicon & Validation: Support pre-silicon emulation (FPGA, Palladium) and post-silicon validation in lab environments to ensure spec compliance.

In this role, you can lead our teams to deliver fully functional "first silicon" IP designs, from defining initial constraints through high-quality tape-out. You will have the rare and rewarding privilege of crafting upcoming products that will delight and inspire millions of customers every single day.
Responsibilities
Own the entire IP-level netlist generation and timing convergence journey, from synthesis and UPF power intent to final sign-off.
Architect and manage complex timing constraints (SDC) for both standard and custom designs, ensuring sign-off quality from day one.
Drive Full Chip and block-level timing/noise convergence, including hierarchical timing flows and power optimizations.
Collaborate closely with RTL designers to understand clock architecture, DFT teams on mode constraints, and PNR teams to achieve flawless physical convergence.
Develop and support automated block and chip-level sign-off flows, working with CAD teams to shape cutting-edge methodologies that eliminate pessimism and accelerate convergence.
Perform deep-dive signal integrity (SI) and noise analysis, drive custom IP integration, and generate block-level budgets to ensure correlation with the Full Chip.

As a Design Verification Engineer, you will be responsible for ensuring "bug-free first silicon" for complex IP and SoC designs. You will drive all phases of pre-silicon verification, from defining methodologies and test plans to RTL freeze and tape-out sign-off. These roles are highly collaborative, requiring close interaction with architecture, design, and software teams across global sites.
Responsibilities
Architect and develop scalable, portable verification environments, including UVM-based testbenches, protocol monitors, agents, and checkers.
Define detailed test and coverage plans based on micro-architecture specifications and extract features for DV attributes.
Create and simulate test scenarios, perform advanced debugging, and conduct end-to-end simulations of data/control paths.
Drive regression and coverage analysis (metric-driven verification) to ensure the highest quality, productivity, and time-to-market.
Partner with architects and designers from the early stages of feature definition to influence IP/SoC specifications.
Apply formal verification, hardware acceleration, and power/performance (NLP) analysis where applicable.

We are seeking for an individual with the skills and motivation to become a data analyst in a global leading company.
You will get the opportunity to work with talented data analysts worldwide, in a variety of topics using different BI tools in an advanced environment.
Key Responsibilities
You will learn the business needs of the various departments in the organization.
Build analytic reports to provide business insights.
Responsible for the ongoing development of the companies reporting catalog.
Initiate advanced analytics projects.

We are looking for a Mid-level Data Engineer to join our growing Data/MLOps team. The team is focused on building a Data/MLOps infrastructure to support the development of ML and AI algorithms for our next generation iTero scanners.
The position is suited for engineers who like to work with data, build data infrastructure and wish to support algorithm engineers.
The position is based at our Petah Tikva or Caesarea site.
Key Responsibilities
Own significant components in a data infrastructure for AI/Algorithm development.
Work with large image/3D datasets to support the development of real-life ML/AI solutions.
Work with ML / AI engineers to identify future challenges and solutions.
Own the quality of data ingestion pipelines over time.
Consistently demonstrate innovative thinking, strong partnership and high work ethics.

In these roles, engineers will be responsible for the design, development, and bring-up of innovative silicon and system solutions across multiple specialized teams. Responsibilities include participating in SW design sessions, providing HLD and LLD documentation, and coding complex modules that serve as the foundation for our device ecosystem. You will lead HW-SW integrations, debug complicated system-wide bugs with limited visibility, and optimize designs for performance, power, and memory footprints while meeting hard-real-time latency requirements.