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Take part in the development of cutting-edge products within a disruptive system architecture. You will have the opportunity to work on the technologies that power the worlds largest cloud provider, in a dynamic, open, and fast-paced environment. AWS provides a highly reliable, scalable, low-cost infrastructure platform in the cloud, which powers hundreds of thousands of businesses in 190 countries around the world. Annapurna Labs, as part of Amazon Web Services (AWS), is looking for talented engineers to help us develop a semiconductor platform based on a revolutionary architecture.

Looking for exceptional senior engineers to join the top-tier team that is developing the next generation semiconductor platform, based on a revolutionary architecture. Engineers will participate in design and verification activities, working on the next generation of our products.

You are invited to take part in developing, integrating and deploying cutting-edge technologies, starting with identification and definition of project requirements, architecture, feature development, and collaboration with the different groups.
Your design will be integrated into the nitro SoC, on millions of servers worldwide. This is an opportunity to have a large-scale impact.
As a VLSI engineer and a member of the Nitro project, you will have an impact over the device through its entire lifecycle, from the product definition stage to mass production. You will work in close collaboration with multiple groups, including Architecture, Software, Verification, Backend, and DFT.

Required Technical Customer Application Engineer
Do you have a passion for cutting-edge automotive technology and a desire to work with the world's leading car manufacturers?
We are seeking a highly motivated and technically skilled Customer Application Engineer to join our team, supporting the integration of our state-of-the-art automotive imaging radar technology into the next generation of vehicles.
Our vision is to bring new and cutting-edge automotive radar sensor solutions, while leveraging Mobileyes assets and expertise in this field. Introducing best in class Radar sensor that would complement Mobileyes end-to-end autonomous driving solution platform. You will be joining an excellent group of people, working on a cutting-edge mmWave Radar Technology and enjoy a dynamic and challenging environment.
What will your job look like?
Establish customer model and support team for a new top-performance product working with top brand European car OEMs
Provide Hands-On & technical support for key automotive customers on complex technical issues
Diagnose and resolve software integration issues in collaboration with customers and internal engineering teams.
Collaborate with customers throughout the development cycle, from initial concept and feasibility studies to product integration and deployment.
Create technical collaterals: application notes, user guide, product documentation
Create variant solutions for customer issues, take proactive actions to ensure customer high satisfaction
Design and integrate customer first level analysis tools
Report customer feedback and requests back to support manager, product group, and R&D.

Do you have a passion for cutting-edge automotive technology and a desire to work with the world's leading car manufacturers?
We are seeking a highly motivated and technically skilled Software and Automation Tools Engineer to join our team.
Our vision is to bring new and cutting-edge automotive radar sensor solutions, while leveraging our assets and expertise in this field. Introducing best in class Radar sensor that would complement our end-to-end autonomous driving solution platform. You will be joining an excellent group of people, working on a cutting-edge mmWave Radar Technology and enjoy a dynamic and challenging environment.
What will your job look like?
You will be Responsible for high-quality, end-to-end, validation / automation infrastructure & tools
Work on data collection & offline processing SW tools to enable Automotive RADAR development.

We are seeking a highly motivated and skilled System Engineer to join our team, focusing on automotive imaging radar systems. This role is pivotal in bridging the gap between our cutting-edge radar technology and our automotive customers' evolving needs. As the key technical focal point, you will lead customer engagements, manage system-level requirements, and ensure successful integration and performance of our radar solutions in real-world automotive applications.
What will your job look like?
Develop system requirements and architecture that align with customer needs
System architectures and flows for critical functions, including boot processes, power-on sequences, system health monitoring, and diagnostics
Engage with customers, analyze and understand customer requirements and maximize alignment with existing solutions.
Program planning with internal and external customers: define, map dependencies, and prioritize the scope of customer releases.

Required Semiconductor Quality and Reliability Engineer
As a Quality and Reliability (Q&R) Engineer, you will lead the qualification and long-term reliability of advanced System-on-Chip (SoC) semiconductor products for automotive applications. Youll work across digital and RF domains to ensure robust performance and compliance with industry standards.
What will your job look like:
Define and manage Quality and Reliability specifications, simulations, and qualification plans for SoC die and package.
Plan and execute automotive-grade qualifications per standards such as AEC-Q100, JEDEC JESD22, and IATF 16949.
Design and implement die-level and package-level stress tests.
Select and prepare electrical, environmental, and mechanical test platforms for reliability testing.
Define requirements for Pre-Si Q&R (e.g. ESD, LU, EM, IR drop), Design-for-Test (DFT), electrical characterization, and Post-Si Q&R testing of digital, mixed-signal and RF SoCs.
Collaborate extensively with internal design teams, external subcontractors, and outsourcing partners (OSATs).
Lead failure analysis, reliability modeling, and corrective action processes (e.g., 8D, FMEA, FMEDA).
Document and certify automotive standards compliance, including PPAP/APQP deliverables.

Were looking for a Physical Design Engineer to join the growing Physical Design Team, responsible for state of the art SoC design from definition to Tape-Out.
What will your job look like:
Hands-on physical design block owner from RTL to GDS.
Floorplan exploration with guidance and collaboration with front-end and architecture teams.
STA: work with FE and floor planner to manage block and top level constraints and 1st level of timing analysis.
Synthesis exploration and final synthesis netlist: Scan insertion @ synthesis, clean checks from Lint, UPF & Spyglass.
Place & Route: from Synthesis netlist to final layout and signoff verification with target to achieve best power performance and area.

Required Experienced SoC Verification Engineer
Which team will you join?
EyeC VLSI team - a group designing the chips for Radar systems for ADAS and autonomous cars. The group is responsible for all disciplines of VLSI development, including but not limited to Logic Design, Design Verification, Microarchitecture, Analog and circuit design and layout, Physical and structural design (backend), Product and test engineering.
What will your job look like:
You will take a central hands-on role in Design Verification.
Define Environment micro-Architect, Implement complex UVM environment, Build vPlan .
Execute coverage implementation.
Be part of external IP verification and Internal custom IP.
Be part of System definition and top-level activity.
Take part in Silicon bring-up.

Our Imaging Radar group develops innovative high-performance Radar solutions for ADAS and Autonomous Driving markets.
We are seeking an experienced SoC Architect to join us.
What will your job look like:
Lead End-to-end life cycle of the Radar System-on-Chip architecture definition and development.
Provide detailed specifications for chip modules and flows.
Work in close collaboration with the various teams, including system, algo, design, verification, backend, firmware, package and post-silicon.

Required Experienced RFIC/Analog CAD Engineer
The RFIC/Analog design groups in our Radar organization is responsible for developing the cutting edge Transceivers in mmW frequencies for the best Imaging Radar technology. The design process includes the entire process from specs to productization.
To support these challenging processes, we need a skilled CAD team that will work with the design teams on all design aspects and flows from design environment setups, through design tools implementations and support and to chip level verifications and validation enablement.
We're looking for an Experienced CAD or Design Automation Engineer to develop our RF/Analog design tools/flows and automation flows for the next-generation Imaging Radar chips.
What will your job look like:
Build and support RF/analog design environments
Implement, develop, and maintain design flows, tools and scripts.
Evaluate and explore new automation technologies and advocate for efficiency improvements
Evaluate multiple vendor solutions and guide execution, in the most optimal use, based on design needs
Effectively communicate and support a large number of designers, providing high-quality tools and flows, documentation, and presentations.

Required Experienced Logic Design Engineer
The EyeC VLSI team specializes in designing advanced radar system chips for ADAS (Advanced Driver Assistance Systems) and autonomous vehicles. The group is responsible for all disciplines of VLSI development, including but not limited to Logic Design, Design Verification, Microarchitecture, Analog and circuit design and layout, Physical and structural design (backend), Product and test engineering.
What will your job look like:
Design ownership on major blocks/clusters from definition to implementation phase.
Participate in various ASIC activities and flow definition which includes CDC, DFT, Lint.
Design micro-architecture of custom blocks.

Required Experienced DFT Engineer
The EyeC VLSI team designs cutting-edge chips for RADAR systems used in ADAS and autonomous vehicles and is looking for an experienced DFT Engineer.
This is a unique opportunity to join a team of top-tier engineers working with the most advanced technologies to develop Autonomous Vehicle (AV) SoCs. Every engineer in our team plays a broad and diverse role, taking on significant responsibilities, being involved in critical development stages, and making a direct impact on the success of our projects.
What will your job look like:
You'll be responsible for the architecture of DFT solutions across the SOC (MBIST, SCAN, ATPG, LBIST and more)
Develop all the necessary RTL for the different modules
Verify and Validate your design in GLS
Develop ATPG patterns to the highest requirements of Functional Safety (ISO26262).
Debug and analyze coverage and yield loss
Support production activities and Si debug.

Were looking for a Backend Engineer to join the growing Physical Design Team, responsible for state of the art SoC design from definition to Tape-Out.
What will your job look like:
Hands-on physical design block owner from RTL to GDS.
Floorplan exploration with guidance and collaboration with front-end and architecture teams.
STA: work with FE and floor planner to manage block and top level constraints and 1st level of timing analysis.
Synthesis exploration and final synthesis netlist: Scan insertion @ synthesis, clean checks from Lint, UPF & Spyglass.
Place & Route: from Synthesis netlist to final layout and signoff verification with target to achieve best power performance and area.

Required SoC Performance Modeling Engineer
The EyeQ SoC Performance Modeling and Profiling team is part of the EyeQ Platform Group (EPG), working on both current and next-generation designs for ADAS (Advanced Driver-Assistance Systems) and Autonomous Vehicles (AV).
Performance models and profiling tools are essential components of the EPG infrastructure they are used during the hardware architecture definition phase of the EyeQ chip and by software developers to optimize performance.
What will your job look like:
You will be part of team that develops SoC Performance Modeling environment and emulators
You will work on SOC performance analysis and optimizations.
You will be running HW benchmarks, to measure HW performance and to calibrate the simulation environment to match the performance of the silicon board.
You will be working on HW performance analysis and tuning, and influence future SoC design.
You will have the opportunity to work on open-source simulation and profiling tools and adopt them to our needs.
You will work closely with HW architects and SW/Algorithms developers.

GNC Engineer (5860).
We are looking for a Guidance, Navigation & control engineer to join our R&D team and take part in the development of advanced autonomous and electromechanical systems.

In this role, you will design, simulate, and implement control and navigation algorithms for dynamic multi-degree-of-freedom platforms. Responsibilities Design and implementation of closed-loop control systems.
Modeling and simulation of dynamic systems (6 DOF).
Development of guidance, estimation, and navigation algorithms (PID, LQR, Kalman Filter, etc.).
Sensor modeling, signal analysis, and noise characterization.
Integration of inertial and external navigation systems (IMU, GPS, magnetometer, etc.).
Work with MATLAB/Simulink and transition to Real-Time Embedded environments.
Perform system analysis, validation, and testing.

We are looking for talented physical design implementation engineers to join our excellent Physical Design team, which develops our next generation of products for the cloud market.

Key job responsibilities:
* Daily involvement in all aspects of physical design chip development (RTL2GDS), including floorplanning, synthesis, clock tree synthesis, place and route, static timing analysis, power and noise analysis, physical verification testing, and equivalence checks.
* Being actively engaged in design-backend convergence aspects and defining timing constraints.
* Taking full end-to-end responsibility for the physical design of macros and clusters level, according to specifications, under challenging constraints, with focus on optimizing power, area, and performance.
* Participation in the development of design flows, using a variety of EDA tools and vendors such as Synopsis and Cadence.
* Engaged in defining implementation and signoff methodologies.