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Required Hardware/Silicon Engineering PhD Intern, 2027
Please complete your application before 23rd October 2026.
About the job
The Cloud and AI Infrastructure team in Israel focuses on building our next-generation systems. The teams work is grounded in creating custom hardware, and as an Intern you'll get to collaborate with engineers from various parts of the organisation to influence the future of Cloud and the AI infrastructure by working on the foundational technology that makes it all possible. This is the hardware that powers everything from Cloud, to our most advanced models like Gemini.
As an intern, you will work on fundamental problems at the intersection of hardware, software, and algorithms. You will collaborate with exceptional engineers and researchers on projects that directly impact our custom silicon portfolio, including general-purpose CPUs, highly specialized AI accelerators like our Tensor Processing Units (TPUs), and complex Systems-on-a-Chip (SoCs). Your responsibilities and projects will be tailored to your expertise and could focus on any part of the system stack. This may include:
Algorithmic Innovation: Developing and analyzing new algorithms that are deeply co-designed with our custom hardware.
Software and Compilers: Building the software stack, compilers, and performance analysis tools that unlock the potential of our unique architectures.
System Architectureand and Modeling: Architecting and modeling future CPUs, TPUs, and SoCs to guide critical design decisions.
Hardware Design and Verification: Contributing to all aspects of silicon creation, from logic design and verification to VLSI physical implementation.
Responsibilities
Responsibilities and detailed projects will be determined based on your educational background, interest, and skills.

As a senior compiler engineer, you will own the design and development of our companys open source based toolchain and graph compiler. You will drive technical solutions end-to-end, deliver compiler capabilities across all our company hardware targets, and help mentor engineers. Our team embraces an AI-agentic development flow, leveraging AI coding agents to accelerate engineering productivity, and we are looking for engineers who champion this approach.
Responsibilities:
Design and develop our companys open source based toolchain targeting custom DSP and NPU architectures.
Drive design and delivery of graph compilation flows: transformations, operator mapping, and code generation.
Champion AI-agentic development practices - integrating AI coding agents into day-to-day engineering workflows.
Own complex components end-to-end, from architecture and design through implementation and delivery.
Provide technical guidance and mentorship to engineers; conduct code reviews.
Collaborate with hardware architecture, algorithms, and software teams globally.
Analyze and optimize toolchain output for performance and correctness across our company processor families.

In this role, you will join our Formal Verification team, executing full verification cycle from architectural definition and FV strategy definition to full execution and final sign-off, utilizing advanced Formal Verification methodologies and tools.
This role allows for independent work, impactful input, and substantial contributions to the VLSI departments verification tasks
Responsibilities:
Develop Formal Test benches and Properties - Write and maintain System Verilog Assertions to formally verify RTL designs using industry-standard formal tools.
Collaborating with Design and Verification Teams.
Contribute to Verification Planning and Coverage.
Define formal verification plans, track progress, and contribute to achieving verification completeness.

As a Wireless Platform Architect, you will play a key role in defining the architecture of our company's next-generation Radio Subsystem (RSS) platforms for wireless technologies including Wi-Fi, Bluetooth and UWB. You will take end-to-end responsibility on the system-level architecture of a complete wireless communication subsystem, including system spec, requirements for implementation teams, definition of interfaces and testing concept.
You will work closely with multidisciplinary development teams and directly with customers, from early system architecture and trade-off analysis through implementation, integration, validation and productization.
Responsibilities:
Define the RSS end-to-end architecture and HW/SW partitioning, including interfaces between the radio, PHY, MAC, CPU/MCU, memories, PMU, clock and reset management (CRM) and other subsystem components.
Define architecture and operational mechanisms for multi-protocol operation and interoperability, including HW interfaces, state machines, control flows and operation sequences.
Define sleep/wake-up modes, testability, security and debug.
Drive PPA optimization and competitive benchmarking of the RSS, with particular focus on low-power operation, silicon area and overall system efficiency.
Work closely with RF, PHY/algorithm, HW, SW/firmware, verification and integration teams, from early system studies and architecture definition through RTL/FPGA validation and system bring-up.
Work directly with customers during technical engagements to define the RSS integration into their SoC and support customers throughout SoC integration, validation and productization, addressing system-level architecture, interoperability and integration challenges.

Required RTL Design Technical Lead, Networking, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As part of our Server Chip Design team, you will use your ASIC design experience to be part of a team that creates the SoC VLSI design cycle from start to finish. You will collaborate closely with design and verification engineers in active projects, creating architecture definitions with RTL coding, and running block level simulations.
In this role, you will contribute in all phases of Application-Specific Integrated Circuit (ASIC) designs from design specification to production. You will collaborate with members of architecture, software, verification, power, timing, synthesis, etc. to specify and deliver high quality SoC/RTL. You will solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with complexity, performance, power and area in mind.
Responsibilities:
Define the block level design documents such as interface protocol, block diagram, transaction flow, pipeline, and more.
Perform RTL development (e.g., coding and debug in Verilog, SystemVerilog, VHDL), function/performance simulation debug, and Lint/CDC/FV/UPF checks.
Participate in synthesis, timing/power, and FPGA/silicon bring-up.
Participate in test plan and coverage analysis of the block and SOC-level verification.
Communicate and work with multi-disciplined and multi-site teams.

Join an agile team working on the most advanced wireless communication solutions, focused on the latest communication standards. You will define the architecture for future products and optimize modem solutions for hardware implementation.
Responsibilities:
Research and define architecture for advanced communication standards.
Define PHY System specifications and architecture for future solutions.
Define low-power architecture.
Work closely with the functional teams (Algorithm, HW/SW, RF, Validation, etc.), from early algorithm study to system validation.
Participate in integration and testing of wireless system solutions, spanning embedded SW, HW and radio.
Support customers engagement and product deployment.

Required Emulation Verification Tech Lead, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Responsibilities
Lead, plan and execute the verification of digital design blocks by understanding specifications and working with design engineers to define key verification scenarios.
Develop, execute, and debug full-chip/system on a chip (SoC) tests on emulation platforms.
Collaborate with design engineers to debug tests and ensure functional correctness of design blocks.
Define and implement various coverage measures to capture stimulus and corner-case scenarios. Work with software and post-silicon validation teams to reproduce failures on emulation.
Drive coverage analysis to identify verification gaps and demonstrate progress towards tape-out. Explore new verification and emulation methodologies and implement them.

We are seeking an experienced Senior LRT Project Engineer to support the delivery of major Light Rail Transit (LRT) project. The role requires strong technical leadership, design management expertise, stakeholder coordination, and the ability to drive engineering solutions in a complex project environment.

:Key Responsibilities
Manage and coordinate engineering and design activities throughout the project lifecycle.
Lead the design management process and monitor design deliverables.
Coordinate with local designers, consultants and contractors.
Engage and collaborate with local and international stakeholders.
Resolve technical conflicts, interface issues, and project challenges.
Support multidisciplinary coordination and project reporting.
Utilize Microsoft 365 tools to manage documentation, communication, and project tracking.

we are looking for a Staff Systems Engineer.
As a Staff Systems Engineer, you will be a critical contributor on our Electrophysiology Systems Engineering team focused on delivering the future in Advanced Imaging. This role will involve a range of responsibilities including but not limited to collaborating and leading teams in the strategy, development and analysis of system architecture, system performance and system integration for our next generation products including various imaging modalities such as echocardiography, CT, MRI, and 3D cardiac mapping. In this role you will be a key member of product development team to bring systems from concept to launch.
Duties and Responsibilities:
Define and influence, and drive execution of technical strategy for system-level programs while partnering with cross-functional stakeholders on business strategy and product roadmaps.
Utilize multidisciplinary engineering knowledge and experience to design, develop, and troubleshoot new products specific to cardiac mapping and advanced imaging.
Provide system engineering leadership and take ownership for overall project success for new products and features from concept phase through launch.
Work with Product Marketing, Clinical Engineering, and Key Opinion Leaders to develop design input requirements from user and business needs.
Communicate with Sr. Management including technical presentations, status updates, and program reviews.
Lead project-level system architecture, system behavior definition, and tradeoff analysis activities utilizing Model-Based Systems Engineering (MBSE) methodologies, including use case modeling, requirements traceability, system architecture modeling, and interface definition.
Lead cross-functional working groups to solve complex problems, mitigate risks, and develop strategies to overcome challenges.
Plan, manage, and report on overall systems integration activities including root cause analysis and solution generation.
Identify, communicate, and proactively manage technical, integration, and program risks throughout the product development lifecycle.
Provide input into the technology and product roadmaps.
Be a strong team player and lead cross-functional teams to resolve issues and meet budget and schedule requirements.
Create a positive, collaborative culture amongst the technical teams while working to solve challenging engineering problems.
Mentor engineers across multiple disciplines and serve as a technical leader driving engineering excellence, sound systems thinking, and effective technical decision-making.
Ensure compliance with procedural and documentation requirements of , FDA, ISO and other regulatory bodies.

Required Junior AI SoC Design Verification Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will join a high-performing Research and Development team dedicated to delivering high-quality silicon. You will partner with cross-functional technical teams throughout the full development lifecycle, taking ownership of quality assurance strategies from the initial concept through final tape-out.
Responsibilities
Plan digital design block verification by analyzing specifications and identifying critical scenarios with design engineers.
Create and enhance constrained-random environments using SystemVerilog and Universal Verification Methodology (UVM), or execute formal verification using SystemVerilog Assertions (SVA) and industry-leading tools.
Identify and write all types of coverage measures for corner-cases.
Debug test failures alongside design teams to ensure block correctness.
Analyze metrics to resolve coverage gaps and drive progress toward tape-out.

we are hiring Integration Engineer / system Engineer A leading company is looking for an Integration Engineer / system Engineer to join a significant technology project in the defense sector. About the Role
* Join a complex and challenging project in an advanced technological environment.
* Work on the integration of systems and various technological components.
* Collaborate with engineering teams, technical interfaces, and professional stakeholders.
* Participate in a dedicated professional training program at the beginning of the role.?? Location The project is based in Modi'in, with potential opportunities to work at additional sites according to project requirements. If you are an engineer with experience in system integration or systems engineering and are looking for an opportunity to join a meaningful project, gain professional expertise, and work in an advanced technological environment - we'd love to hear from you!

we are looking for a Product Engineering.
Transition of products from development to production
Subcontractors production lines support & training
Lead & Implement DFXs methods
Driving corrective & preventative actions

the global innovator and leading solutions provider of 5G wireless transport, is looking for an Algorithms Engineer to join our team.
In this role you will:
Be a part of a leading Algorithm team responsible for developing Radio core technologies for innovative wireless communication products.
Develop algorithms and architectures for a high spectral efficiency modem in a challenging environment.
Simulate and test new HW & SW designs in Matlab and real-time, in a full modem and channel environment.
Collaborate with the VLSI, RF, SW and System groups.
Take end-to-end ownership, from the concept stages to the fully operational system.

we are looking for a RF System Architect.
The wireless system engineer is a key position in a multidisciplinary R&D organization and acts as a technical lead for all matters related to wireless system design in new and existing products.
In this role you will be part of a dynamic team responsible for defining the architecture of a product, targeted to the Wireless Backhaul Market for 5G deployments.
Understand and analyze customer needs and market trends.
Define hardware, firmware and software requirements while supporting other R&D and Engineering teams, during all project phases.
Support field trials, customer challenges and production processes.