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You will be part of our company's REM department. our companys Road Experience Management (REM) is an end-to-end mapping and localization engine which is used for full autonomy capabilities and services. Generating validation process and methodologies for such a technology giant is challenging, sufficient & enriching work. Since we are dealing with a complex system based on machine learning and image processing, the analysis and validation processes require deep thinking as well as advanced technical and analytic abilities. You will be responsible for defining and developing validation infrastructure, tools and methods using cutting edge technology and cloud-based application.
What will your job look like?
Participate in planning and implementation of advanced validation Processes
Define and implement end-to-end validation tools and methods with advanced geometric calculations, logics, and heuristic
Integrating new features into existing Validation Processes
Improving sensitivity, efficiency, effectiveness, and quality of validation processes
Management and prioritization of daily tasks
Integration of tools and algorithms from different departments in the company and applying them into our validation infrastructure.

we are looking for a Embedded SW Engineer for Performance Modeling. You will be part of EyeQ SoC Performance Modeling and Profiling team in EyeQ Platform Group (EPG), working on current and next-generation designs for ADAS/AV. Performance models and profiling tools are fundamental parts of the EPG infrastructure, they are used during EyeQ HW architecture definition phase and by SW developers for performance optimizations.
What will your job look like:
You will work on CPU functional and timing models of our company's SoC platforms.
You will work on developing tracing and profiling tools for CPU performance analysis and optimizations.
You will run HW benchmarks to test HW performance and calibrate the simulation performance with the silicon board.
You will have the opportunity to work on open-source simulation and profiling tools and adopt them to our company's needs.
You will work closely with HW architects and SW/OS/Algorithms developers.

our company's Automated Driving group in Haifa is looking for an experienced DFT Engineer. This is an exciting opportunity to join a team of highly talented engineers, working on one of the most cutting edge technologies - Autonomous Vehicle (AV) SoC. At our company's Automated Driving group, we know that the idea of a fully autonomous car is no longer science fiction, but a reality that we are creating! We have spent more than 15 years developing the world's most Advanced Driver Assistance Systems (ADAS) and we are now leading the computer vision and machine learning domain, reaching fully automated driving experience (AV).
What will your job look like:
You'll be responsible of architecture of the DFT solutions across the SOC (MBIST, SCAN ATPG, LBIST and more)
Develop all the necessary HW / FW / SW for the different modules
Verify and Validate our design
Debug and analyze coverage and yield loss
As a cutting edge technology company, we are working only with the very advanced DFT tools and features, while developing our own methods and DFT concepts as it required by the Automotive and Safety related products market (ISO26262).

Were looking for a Site Reliability Engineer (SRE) to join the R&D team
WHAT YOULL DO

Work closely with R&D engineers on coordination, communication, and execution of production-related operations
Maintain a safe and healthy production environment by following and enforcing standards and procedures
Work in an agile & fast-growing environment
Identify operational problems by observing and studying system functioning and performance results
Provide operational management information by collecting and analyzing operating and engineering data and trends
Constantly improve the technology stack, supporting the data growth and customer requirements
Work with cutting-edge technologies in a dynamic and agile environment

our company's Automated Driving group in Haifa is looking for an experienced DFT Engineer. This is an exciting opportunity to join a team of highly talented engineers, working on one of the most cutting edge technologies - Autonomous Vehicle (AV) SoC. At our company's Automated Driving group, we know that the idea of a fully autonomous car is no longer science fiction, but a reality that we are creating! We have spent more than 15 years developing the world's most Advanced Driver Assistance Systems (ADAS) and we are now leading the computer vision and machine learning domain, reaching fully automated driving experience (AV).
What will your job look like:
You'll be responsible of architecture of the DFT solutions across the SOC (MBIST, SCAN ATPG, LBIST and more)
Develop all the necessary HW / FW / SW for the different modules
Verify and Validate our design
Debug and analyze coverage and yield loss
As a cutting edge technology company, we are working only with the very advanced DFT tools and features, while developing our own methods and DFT concepts as it required by the Automotive and Safety related products market (ISO26262).

The company's EyeC VLSI team designs cutting-edge chips for RADAR systems used in ADAS and autonomous vehicles and is looking for an experienced DFT Engineer. This is a unique opportunity to join a team of top-tier engineers working with the most advanced technologies to develop Autonomous Vehicle (AV) SoCs. Every engineer in our team plays a broad and diverse role, taking on significant responsibilities, being involved in critical development stages, and making a direct impact on the success of our projects.
What will your job look like:
You'll be responsible for the architecture of DFT solutions across the SOC (MBIST, SCAN, ATPG, LBIST and more)
Develop all the necessary RTL for the different modules
Verify and Validate your design in GLS
Develop ATPG patterns to the highest requirements of Functional Safety (ISO26262).
Debug and analyze coverage and yield loss
Support production activities and Si debug.

The company's EyeC VLSI team designs cutting-edge chips for RADAR systems used in ADAS and autonomous vehicles and is looking for an experienced DFT Engineer. This is a unique opportunity to join a team of top-tier engineers working with the most advanced technologies to develop Autonomous Vehicle (AV) SoCs. Every engineer in our team plays a broad and diverse role, taking on significant responsibilities, being involved in critical development stages, and making a direct impact on the success of our projects.
What will your job look like:
You'll be responsible for the architecture of DFT solutions across the SOC (MBIST, SCAN, ATPG, LBIST and more)
Develop all the necessary RTL for the different modules
Verify and Validate your design in GLS
Develop ATPG patterns to the highest requirements of Functional Safety (ISO26262).
Debug and analyze coverage and yield loss
Support production activities and Si debug.

Were looking for a Solutions Engineer  to join us
WHAT YOULL DO

Partner with the sales team to provide technical leadership to our customers and prospective customers while helping your team meet their quarterly sales targets.
Give presentations to our customers and prospective customers, such as whiteboards, product demonstrations, slides, and proof of value outcomes.
Help our customers and prospective customers plan in-depth test plans for showing the value of the platform in their environment.
Invest time in learning new product features, industry-related developments, and broadening your overall technical skill set.
Represent in technical forums, such as trade shows, technical meetups, and industry events.

You will join the IMS core embedded development team, which is responsible for designing, building, and developing a Real-Time software application running within the company's unit. You will have an opportunity to influence the design and implementation of our company's IMS products, which will improve the safety of thousands of vehicles worldwide.
What will your job look like:
Lead new features end-to-end from high and low-level design for a real-time complex system.
Participate in design review sessions.
Develop and integrate your designed modules in C++ and sometimes Python.
Improve existing modules.
Work with other team members.
Work closely with other development, product management, and support teams.

As an Information Systems developer and implementer, you'll be an integral part of the Integration team and you will design, develop, implement, and support integrations based on users' requirements.We are looking for a strong developer with hands on experience to build integrations, currently using the iConduct platform as our main integration tool. And serve as a professional lead in driving the units adoption of new integration systems. We are looking for a strong developer with hands on experience to build integrations, currently using the iConduct platform as our main integration tool. And serve as a professional lead in driving the units adoption of new integration systems.
What your job will look like?
Build integration architecture for all information systems and execute them.
A hands-on developer creating on going integrations, scripts and automation with the growing our company ecosystem.
Collaborate with teams across the organization to gather requirements to improve their day-to-day work.
Creating and maintaining automated post-procedure tools to maintain our company's business efficiency while improving existing processes.
Maintaining the integrity and smooth functioning of the company's integration architecture.

The company's EyeC VLSI team specializes in designing advanced radar system chips for ADAS (Advanced Driver Assistance Systems) and autonomous vehicles. The group is responsible for all disciplines of VLSI development, including but not limited to Logic Design, Design Verification, Microarchitecture, Analog and circuit design and layout, Physical and structural design (backend), Product and test engineering.
What will your job look like:
Design ownership on major blocks/clusters from definition to implementation phase.
Participate in various ASIC activities and flow definition which includes CDC, DFT, Lint.
Design micro-architecture of custom blocks.

The company's EyeC VLSI team specializes in designing advanced radar system chips for ADAS (Advanced Driver Assistance Systems) and autonomous vehicles. The group is responsible for all disciplines of VLSI development, including but not limited to Logic Design, Design Verification, Microarchitecture, Analog and circuit design and layout, Physical and structural design (backend), Product and test engineering.
What will your job look like:
Design ownership on major blocks/clusters from definition to implementation phase.
Participate in various ASIC activities and flow definition which includes CDC, DFT, Lint.
Design micro-architecture of custom blocks.

The company's EyeC VLSI team designs chips for RADAR systems used in ADAS and autonomous vehicles. Our Physical Design team operates in a startup-like environment, emphasizing technical expertise, execution, and ownership. Each engineer in the Physical Design team takes full responsibility for their work, from initial definition through execution and final sign-offs. Engineers collaborate closely with design and architecture teams to develop constraints, conduct design reviews, and implement RTL modifications to ensure convergence. We are seeking an Experienced Backend to join our growing Physical Design team. In this role, you will play a key part in the design of state-of-the-art SoCs, from definition to Tape-Out.
What will your job look like:
Hands-on physical design block owner from RTL to GDS.
Floorplan exploration with guidance and collaboration with front-end and architecture teams.
STA: work with FE and floor planner to manage block and top level constraints and 1st level of timing analysis.
Synthesis exploration and final synthesis netlist: Scan insertion @ synthesis, clean checks from Lint, UPF & Spyglass.
Place & Route: from Synthesis netlist to final layout and signoff verification with target to achieve best power performance and area.
Signoff : on all physical design domains- STA, IR/EM, Physical Verification, Logic Equivalent Checking, Low Power Verification.

our company's EyeC VLSI team - a group designing the chips for RADAR systems for ADAS and autonomous cars. Our Physical Design group is working in a Startup like environment with respect to technical expertise, execution & responsibility . Each Physical Design engineer has an end to end responsibility from definition, execution & full signoffs, working closely with design & architecture teams for constraints development, design review & RTL modifications to achieve converges Were looking for a Experienced Physical Design Engineer to join the growing Physical Design Team, responsible for developing our next generation Imagining Radar SoC from definition to Tape-Out.
What will your job look like:
Hands-on physical design block owner from RTL to GDS with horizontal ownership.
Floorplan exploration and collaboration with front-end and architecture teams.
Synthesis exploration and final synthesis including: SDC definition, Scan insertion, Lint, LEC, UPF-LP & Spyglass verification.
Place & Route: from Synthesis to final layout and signoff verification on all tools and floors, with target to achieve best PPA.
STA: timing analysis, working with Sub System and Full Chip owners to manage block and top level constraints for synthesis, P&R and signoff.

Our vision is to enable the autonomous vehicle dream with best in class, cutting-edge, imaging radar. We are looking for an Experienced RFIC/MMWIC Engineer to join the development of the next generation of RF silicons that are part of a Software Defined Radar. The group hosts a diverse team of scientists, engineers and developers to research, realize and bring to market innovative new silicons. You will be part of a winning RF design team in a fast-paced startup-like environment, working on many different RF and analog components of the RF silicons in the most advanced nano-scale Technologies.
What will your job look like?
R&D of RF chip design in a mass production process.
Time + Frequency domain analysis of RF circuits.
Complete the Design process from spec review to design and lab support.
Design of different RF passive and active structures in the chip level.
Interface with RF architects, hardware designers and test engineers.