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we are now looking for a formal verification manager to join our networking team!
as a formal verification manager in networking business unit, you will lead a team of highly skilled formal engineers responsible for verifying the next generation of cutting-edge network products and gpu technologies.
this is a unique opportunity to make a real impact at the heart of ai and hpc revolution, while working in a fast-paced, innovative environment.
you will be part of a passionate and experienced team using leading formal verification tools and methodologies to ensure design correctness at the highest level. your work will influence key architectural decisions and help deliver world-class silicon solutions for data centers, high-performance computing, networking, and Storage applications.
what youll be doing:
lead and grow a team of formal Verification engineers focused on pre-silicon formal verification of complex digital designs.
define and drive formal verification strategies and methodologies to prove the correctness of designs across multiple projects.
collaborate closely with architecture, design, dv teams to identify verification needs and drive closure.
provide technical guidance, mentoring, and support to engineers in the team.
own the planning and execution of formal verification deliverables to ensure high quality and timely tapeouts.

we are looking for best-in-class physical design power engineer to join our outstanding networking silicon power engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput, lowest latency and best power! come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
what you will be doing:
power optimization of physical design, of blocks/top-level/fc under challenging constraints.
optimization involves all aspects of physical design chip development (rtl2gds) - synthesis, power and clock distribution, place and route, timing closure, power and noise fixes.
power estimation and power modeling.

we are hiring a skilled senior dpu performance Validation engineer for our dpu product lines. this includes chip architecture performance characterization, debug, and validation across single-die and multi-die systems. working in the network silicon engineering group, you will be responsible for debugging, analyzing, and validating performance and functional behavior of current and future silicon devices. you will collaborate with chip design, verification, fw, and architecture teams to ensure successful product development with bold product cycles. the qualified candidate should be comfortable working in simulation and emulation environments, with strong skills in rtl-level debug, waveform analysis, and system -level performance root cause analysis.
what you will be doing:
learn and analyze system -level operation of dpus
debug and root-cause performance issues in pre-silicon environments, across rtl, waveform traces, and multi-die system simulations.
collaborate closely with design, verification, architecture, and performance modeling teams to isolate and fix issues.
develop and improve validation methodologies for performance experiments and data collection.
automate repetitive debug and validation tasks to scale coverage and efficiency.

ethernet switch firmware team is looking for a hardworking firmware manager to take part in leading and developing the firmware / hw interface in the next generation state of the art switch products.
as a member of our fw ethernet team, you will be responsible on a team of firmware engineers. it is expected that you will manage and guide the team for critical items.
this role offers you an excellent opportunity to accomplish something new, enabling understanding of hw and sw in a rapidly growing field while solving interesting technical issues and providing feedback to the hw team to improve the next asic generation.
what you will be doing:
lead a team of engineers and provide technical guidance to the team of highly skilled engineers. empower the team members to excel and increase team productivity.
lead the design and implementation of new features in the core of switch networking firmware.
drive and facilitate the planning, scheduling, and execution of the project and activities of the team
collaborate with architecture and different software design teams as part of the software development lifecycle.
work in pre and post-silicon development environments of next-generation switch networking products.
gain a deep understanding of networking technology, system debugging, and stacks, as well as the hw/fw/sw relationship.
innovate! bring networking products to shine in customers view

we are seeking a dedicated firmware engineer to join our nic firmware core team in beer-sheva/tel-aviv. you will contribute to the development of brand-new networking adapter technologies, elevating the performance of current and future our company devices. our company develops innovative and next-generation networking devices that are known for their outstanding performance and power efficiency. the position involves all aspects of firmware development, including design, micro-architecture, software interfaces, and verification. we are seeking a dedicated and motivated engineer who will contribute to the development of advanced technology network adapters. you will also have the opportunity to create features for leading cloud computing providers and high-performance computing networks.
what youll be doing:
take a part in the design, development, TEST, debug, and optimization of low-level firmware layer on next-generation network adapters up to package release
analyze, integrate, support, and debug low-level firmware layer on verification environments
collaborate with firmware, software, and architecture teams to analyze, design, and debug legacy and new low-level firmware flow
improve our team processes including design and implementation of new methodologies, automated processes.

we are looking for best-in-class physical design engineers to join our outstanding networking silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
what you'll be doing:
perform advanced static timing analysis (sta) for hsio at chiplet and fc level.
running prime time, review and debug timing paths, understand constraints, sdc generation, timing ecos generation.
identify convergence risks and work closely with physical design, rtl and dft teams, ensuring convergence throughout various project stages.
responsible for a full timing closer and quality approval from pre-layout sta model through signoff.
ai use for timing optimization and data analysis.

we are looking for best-in-class chip design engineers to join our outstanding networking silicon engineering team, developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! come and take a significant part in designing and verifying our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a huge impact in a technology-focused company.
what you will be doing:
join beer-sheva/tel-aviv group, working on design in the field of encryption accelerators.
design of chip blocks/entities according to specifications under challenging constraints and with high orientation to power, area and performance.
daily work will involve design and might involve any or all aspects of chip development including design and micro-architecture.
work closely with firmware and other groups around the globe.
work mode: hybrid home-office

we are looking for best-in-class physical design engineers to join our outstanding networking silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
what you'll be doing:
physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.
be exposed and work on a variety of exciting designs. resolving complex timing and congestion problems.
daily work involves all aspects of physical design chip development (rtl2gds) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
taking part in flow development.

are you passionate about working on a team that is at the cutting and bleeding edge of hardware technology? our design-for- TEST engineering team works on groundbreaking innovations involving crafting creative solutions for dft architecture, verification and post-silicon validation on some of the industry's most sophisticated semiconductor chips. we are looking for a dft engineer to join the atpg team. the position includes taking part in development of the next generation dft technologies and working closely with a wide range of our groups and aspects - chip design, backend, verification, and production testing.
working on the most advanced technologies and complex products, our dft solution are unique and innovative internal developments, and we are continuously improving and evolving the solution to meet the challenging goals. if you find groundbreaking technologies, and next generation products interesting, then this is the team for you. take opportunity to join our team for an exciting and educational environment, where every individual has significant contribution to our products and achievements!

we are looking for best-in-class chip design engineers to join our outstanding networking silicon engineering team, developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! come and take a significant part in designing and verifying our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a huge impact in a technology-focused company.
what you will be doing:
join tel-aviv/beer-sheva group, working on verification in the field of encryption accelerators.
verification of chip blocks/entities according to specifications under challenging constraints and with high orientation to power, area and performance.
daily work will involve verification and might involve any or all aspects of chip development including micro-architecture.
work closely with firmware and other groups around the globe.
work mode: hybrid home-office.

we are looking for best-in-class chip design engineers to join our outstanding networking silicon engineering team, developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! come and take a significant part in designing and verifying our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a huge impact in a technology-focused company.
what you will be doing:
join beer-sheva/tel-aviv group, working on design in developing riscv core for network accelerators.
design of chip blocks/entities according to specifications under challenging constraints and with high orientation to power, area and performance.
daily work will involve design and might involve any or all aspects of chip development including design and micro-architecture.
work closely with firmware, software and other groups around the globe.
work mode: hybrid home-office.

we are seeking best-in-class asic Verification engineers to help deliver the worlds leading cpu's and SOC 's. this position offers you the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. we are a learning machine that constantly evolves by adapting to new opportunities that are hard to pursue, that only we can take on, and that matter to the world. we have crafted a team of excellent people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.
we are building a new group in israel, this group delivers security engines and risc-v processor ips to all of product lines working with all groups around the world. we are looking for inquisitive, motivated engineers with experience to continue to build this new group. as a senior member of our team, you will be responsible for the verification of high-performance, low-power security engines and risc-v processor modules. you will work closely with architects, design engineers, fc Verification engineers, and sw teams.

the complexity of the chip has greatly increased over the years. we are now packing tens of billions of transistors in a chip to meet the growing computing demand in a footprint that is responsible to our environment. the company system -on-chip design group (socd) is looking for a top asic engineer with a curiosity about SOC design automation, rtl integration, chip build and assembly, and padring design and verification. you should have real passion for methodologies and automation solutions that enable SOC creation in the most optimized way.
in this position, you will get the opportunity to build complex networking chips and interact directly with unit-level asic, physical design, cad, package design, software, dft and other teams. 
what you'll be doing:
implement chip level design through collaboration with cross-functional teams (functional design, dft, design verification, system verification, sta, and physical design).
be exposed and work on a variety of functional and structural challenges. including functional debug, physical design readiness, emulation, resolve design quality issues.
daily work involves aspects of chip level design, including partitioning, cdc, rdc, trial synthesis, design quality checks
taking part in flows development and deployment.

we have been transforming computer graphics, pc gaming, and accelerated computing for more than 25 years. its a unique legacy of innovation thats fueled by great technology-and amazing people. today, were tapping into the unlimited potential of ai to define the next era of computing. an era in which our gpu acts as the brains of computers, robots, and self-driving cars that can understand the world.
the complexity of the chip has greatly increased over the years. we are now packing tens of billions of transistors in a chip to meet the growing computing demand in a footprint that is responsible to our environment. thesystem -on-chip ( SOC ) group is seeking a top SOC Verification engineer to verify the design and implementation of the worlds leading networking socs. in this position, you will get the opportunity to craft complex networking chips and interact directly with architects, designers, and software engineers across sites. this is your chance to shape the future of computing with a world-class team! as an SOC Verification engineer, you will verify the design and implementation of our SOC technologies in various projects. this position offers the opportunity to have real impact in a dynamic, technology-focused company impacting switches and nic SOC product lines. we are working closely with a wide range of aspects - chip design, dft, backend, verification and production testing. we are working on the most advanced technologies and complex products. our SOC solutions are unique, innovative, and we are continuously looking for new and creative solutions to meet the challenging goals.
what you'll be doing:
in this position, you will be responsible for verification of the clock design elements, architecture and micro-architecture using sophisticated verification methodologies.
as a member of our SOC verification team, you'll understand the design & implementation, define the verification scope, develop the verification infrastructure (testbenches, bfms, checkers, monitors), execute TEST /coverage plans, and verify the correctness of the design.
collaborate with architects, designers, emulation, production testing and silicon verification teams to accomplish your tasks.

the complexity of the chip has greatly increased over the years. we are now packing tens of billions of transistors in a chip to meet the growing computing demand in a footprint that is responsible to our environment. the company system -on-chip ( SOC ) group is looking for a top asic engineer with a curiosity about SOC design automation, rtl integration, chip build and assembly, and padring design and verification. you should have real passion for methodologies and automation solutions that enable SOC creation in the most optimized way.
in this position, you will get the opportunity to build complex networking chips and interact directly with unit-level asic, physical design, cad, package design, software, dft and other teams.
what you'll be doing: implement chip level design through collaboration with cross-functional teams (functional design, dft, design verification, system verification, sta, and physical design).
be exposed and work on a variety of functional and structural challenges. including functional debug, physical design readiness, emulation, resolve design quality issues.
daily work involves aspects of chip level design, including partitioning, cdc, rdc, trial synthesis, design quality checks
taking part in flows development and deployment.