לוח משרות דרושים חשמל ואלקטרוניקה בחיפה וסביבתה

we are looking for forward-thinking, self-motivated engineers who thrive in fast-paced environments and "crisis times." Beyond technical excellence, successful candidates are:
Intrinsically, see the importance of every detail in "elegant solutions."
Excellent interpersonal and communication skills to work across diverse functional areas.
Schedule-driven with a desire to solve challenges that have never been solved before.
Responsibilities
Micro-Architecture & RTL: Design and implement high-quality, power-efficient RTL (Verilog/SystemVerilog) from block-level to sub-system levels.
Cross-Functional Collaboration: Partner with Architecture, Algorithm, Software, and Physical Design (PD) teams to translate product requirements into GDS-ready silicon.
Front-End Flow Management: Take ownership of "correct-by-construction" design tasks, including Synthesis, Lint, CDC/RDC (Clock/Reset Domain Crossing), and STA (Static Timing Analysis).
Verification Support: Work closely with Design Verification (DV) and Formal Verification teams to define coverage requirements, develop testbenches, and debug functional/performance issues.
Post-Silicon & Validation: Support pre-silicon emulation (FPGA, Palladium) and post-silicon validation in lab environments to ensure spec compliance.

In this role, you can lead our teams to deliver fully functional "first silicon" IP designs, from defining initial constraints through high-quality tape-out. You will have the rare and rewarding privilege of crafting upcoming products that will delight and inspire millions of customers every single day.
Responsibilities
Own the entire IP-level netlist generation and timing convergence journey, from synthesis and UPF power intent to final sign-off.
Architect and manage complex timing constraints (SDC) for both standard and custom designs, ensuring sign-off quality from day one.
Drive Full Chip and block-level timing/noise convergence, including hierarchical timing flows and power optimizations.
Collaborate closely with RTL designers to understand clock architecture, DFT teams on mode constraints, and PNR teams to achieve flawless physical convergence.
Develop and support automated block and chip-level sign-off flows, working with CAD teams to shape cutting-edge methodologies that eliminate pessimism and accelerate convergence.
Perform deep-dive signal integrity (SI) and noise analysis, drive custom IP integration, and generate block-level budgets to ensure correlation with the Full Chip.

As a Design Verification Engineer, you will be responsible for ensuring "bug-free first silicon" for complex IP and SoC designs. You will drive all phases of pre-silicon verification, from defining methodologies and test plans to RTL freeze and tape-out sign-off. These roles are highly collaborative, requiring close interaction with architecture, design, and software teams across global sites.
Responsibilities
Architect and develop scalable, portable verification environments, including UVM-based testbenches, protocol monitors, agents, and checkers.
Define detailed test and coverage plans based on micro-architecture specifications and extract features for DV attributes.
Create and simulate test scenarios, perform advanced debugging, and conduct end-to-end simulations of data/control paths.
Drive regression and coverage analysis (metric-driven verification) to ensure the highest quality, productivity, and time-to-market.
Partner with architects and designers from the early stages of feature definition to influence IP/SoC specifications.
Apply formal verification, hardware acceleration, and power/performance (NLP) analysis where applicable.

This is a highly visible role where you will own the physical design cycle at the partition, IP, and Chip levels-enabling us to produce fully functional "first silicon" designs. Do you love working on challenges that no one has solved yet? If you are ready to join the world's leading engineers and work with state-of-the-art design flows, come join our group.
Responsibilities
You will be responsible for all phases of pre-silicon development, from initial definition to high-quality tape-out (Netlist to GDSII).
Lead block-level Place & Route (PnR), complex floor-planning, partitioning, and the creation of power domains and grid specifications.
Develop and validate high-performance, low-power clock network guidelines and distribution.
Drive static timing closure (STA), Physical Verification (DRC/LVS), and Electrical/Power analysis (EM, IR-Drop, Xtalk, and Noise).
Participate in establishing CAD and physical design methodologies for "correct-by-construction" designs and assist in flow development for chip integration.
Generate and implement ECOs to fix timing, noise, and EM/IR violations while meeting strict area and power constraints.
Work closely with logic design teams on SoC architecture and HDL (Verilog) to implement timing fixes and design optimizations.

we are looking for a Hardware Lead Engineer.
As HW Lead Engineer, in the Nitro team, you will be responsible for defining Annapurna Labs Smart Network Interface Card (NIC) design, leading development and validation cycles, and bringing the product to healthy mass production.
Youll provide leadership in new technologies, bringing them to large-scale deployment, in a continuous effort to deliver a world-class customer experience. We offer a fast-paced, intellectually challenging position, where youll work with technical experts, senior leaders, covering multiple technologies. We are changing the industry, and looking for individuals who are ready for this challenge and want to reach beyond what is possible today.
Key job responsibilities:
- Define the architecture and design specifications of next generation K2 Nitro Cards.
- Own full product life cycle, engage with design partners and manufacturing sites to enable high-yield mass production.
- Lead the analysis and debugging of complex design, manufacturing, and integration challenges.
- Continuously design for process optimization to improve product quality, simplify workflows, and accelerate the Nitro card development lifecycle.

We are seeking an experienced Senior Engineering-manager with program management capabilities to help us maintained our leading cloud platforms.
Our success depends on our world-class server infrastructure;
we're handling massive scale and rapid integration of emergent technologies.
The ideal candidate will be an experienced engineer who is skilled in managing product development and pushing teams across several geographic regions using a variety of suppliers (CM, ODM/IHV).
The successful candidate will be an innovative self-starter and leader. The candidate will be familiar with the cloud computing industry and AWS offerings and will be passionate about providing the best possible customer experience at the best cost.
The candidate will have an obsession with data and precise analysis and will use these as inputs to make decisions.
Key job responsibilities:
As an Engineering-manager with program management capabilities on the Server Hardware Engineering team you will be responsible for maintaining multiple simultaneous hardware product programs in a highly cross-functional environment which includes internal customers, external vendors and technology partners.
You'll provide leadership to large scale server deployments in a continuous effort to deliver a world-class customer experience at a world-class cost point.
This is a fast-paced, intellectually challenging position, and you'll work with thought leaders in multiple technology areas.
You'll have high standards for yourself and everyone you work with, and you'll be constantly looking for ways to improve your product's performance, quality and cost.
Using data and key metrics, you will also drive and measure process improvements that enhance our operational effectiveness.
You will work independently in a dynamic, challenging, and fast-changing organization.
We're changing an industry, and we need individuals who are ready for this challenge and who want to reach beyond what is possible today.

As a Team Lead, you will lead and mentor a backend development team working on a complex, large-scale medical imaging platform. This role combines Agile leadership with hands-on technical contribution, driving high-quality software delivery in a regulated, customer-focused environment.

Your role

You will act as the Agile facilitator and technical leader of a Radiology Informatics backend team within Philips Image Management in Israel. You will guide the team in delivering scalable, high-performance software that supports advanced PACS solutions used by hospitals worldwide.
Serve as Scrum Master, ensuring effective adoption and continuous improvement of Agile (SAFe) practices
Lead team planning and execution toward iteration and program objectives
Contribute up to 50% hands-on software development and drive technical decision‑making.
Drive complex development efforts and resolve technical blockers
Promote clean, scalable, high-quality code and strong engineering standards
Ensure compliance with development processes, quality metrics, security, and regulatory requirements
Encourage system thinking, domain knowledge, and strong customer focus
Provide clear accountability, remove impediments, and act as an escalation point
Drive innovation through technical reviews, best practices, modern engineering approaches, and the adoption of AI development tools to enhance productivity and code quality
Collaborate with global cross-functional teams and stakeholders
Develop team capabilities through mentoring, delegation, and structured execution.