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You'll be joining our Physical Design team , which is at the center of the silicon development at Cisco. Our engineers deal with all chip design aspects: definition, architecture, micro-architecture, design, verification, signoff and validation.

We use the latest silicon technologies and processes to build the largest scale and most complex devices at the edge of feasibility.

In this role, you will be part of the Silicon One Switch ASIC Post-Silicon Electrical Validation (EPSV) team.
* Ensure the ASIC operates according to specifications and reliably over time by performing extensive, high-precision measurements using advanced test equipment and procedures.
* Conduct deep-dive investigations, integrating knowledge across hardware, software, and system domains to identify root causes of observed device behavior.

* Handle all chip validation aspects, including:
* Building validation plans.
* Deloping ASIC software test infrastructure.
* Writing tests in Python/C++ over device SDK.
* Executing tests and analyzing results.

looking for a talented and experienced engineer to participate in the physical design of the companys product for leading one of BE projects. This position involves working with external back-end developers as well as carrying out critical tasks in-house, and leading aggressive back-end initiatives to meet challenging targets in terms of area, timing, and layout. In this role, you will be at the center of the companys design efforts and will have a significant influence on product architecture.

join our company outstanding team and contribute to our legacy of innovation in the senior product quality and reliability role! at our company , we are dedicated to pushing the boundaries of pioneering technology. the senior product quality and reliability engineer will provide leadership and management for the networking system product quality within the organization. establish, maintain, and optimize an effective quality management methods and target to achieve high quality performance.
as part of our team, you will work on networking system products and ensure their readiness for high-volume manufacturing. leading and mentoring root cause analysis for issues related to design, manufacturing or customers. enhance and improve products performance by proactive risk assessment and other prevention methods. this is an outstanding opportunity to be part of a company that is crafting the future of ai and computing.
 
what youll be doing:
own product quality and reliability performance of networking system products. providing leadership expertise in product performance and quality.
maintain and monitor product health thru structured routines and metrics, enable effective alert mechanism for early identification 
lead structured problem solving and risk assessment for quality issues originating from production and customer. ensure product readiness for hvm manufacturing and scale
responsible for customer quality issues and working within organization to resolve
lead critical processes for product performance e.g - crb, pcn ; non conforming material review - mrb
drive continues improvement initiatives in design, verification and validation processes, manufacturing quality throughout the entire product life cycle and improvement plan.

we are looking for a creative and independent TEST engineer with hands-on experience in digital TEST content development (atpg, lbist, mbist).our high-speed networking products are industry leaders, continually redefining speed, bandwidth, and reliability across generations.
in this role, you will be responsible for developing, validating, and supporting digital TEST content for our advanced network silicon ics (switches, nics, smartnics). you will work closely with dft, design, and TEST engineering teams to ensure high-quality and scalable TEST content from wafer to final product.
what you'll be doing:
develop atpg, lbist, and mbist content based on dft architecture
run validation flows (simulation/emulation/silicon), analyze failures, and debug pattern issues
collaborate with dft teams to ensure alignment between TEST logic and content implementation
support TEST program bring-up and pattern integration on production testers
continuously improve coverage, pattern quality, and pattern generation efficiency
work with product and TEST engineering to support yield improvement and debug activities

you will be developing physical design, sta, logic eq, power integrity flows and methodologies for implementation of networking chips and socs.
work closely with block owners, full chip sta engineers to assure high quality and timely convergence.
come up with unique and creative solutions to the state of the art physical design problems that are needed for our chips.
additional responsibilities include participating and developing flow and tool methodologies for timing analysis and closure, power and noise analysis, ir-drop, em and back-end verification across multiple projects.

looking for a highly motivated Hardware Engineer to lead change impact analysis activities related to engineering design changes (ecos/ecrs) across our cutting-edge networking and computing platforms. this role is critical to ensuring that all product modifications are seamlessly evaluated for their impact on hardware, mechanical design, system performance, and TEST coverage across the product lifecycle. you will work closely with r&d, mechanical engineering, manufacturing, quality, and TEST teams to assess risks, define mitigations, and maintain excellence in product integrity and testability.
what youll be doing:
leading engineering change analysis (eco/ecr) processes across complex hardware systems.
evaluating the impact of component, layout, and mechanical changes on hardware functionality, manufacturability, and testability.
collaborating with cross-functional teams to ensure smooth implementation of changes without compromising product quality.
supporting dft (design for testability) requirements in the face of ongoing design changes.
reviewing bom and layout revisions and assessing ripple effects on power delivery, signal integrity, and thermal performance.
maintaining change traceability and documentation to meet engineering and compliance standards.
coordinating with manufacturing and operations teams to ensure product readiness and alignment with production timelines.

testing electro-optical and electrical chips and systems.
link-level performance characterization, verification, and debugging.
responsibility for complicated setups establishments, covering both optical and electrical components
characterizing optical and electrical performance using lab equipment and sw tools.
take an active part in silicon bring-up while managing e2e testing of the newest asics, with the objective of driving product to mass production with first-in-class performance.
characterizing products performance using lab equipment, such as oscilloscope, spectrum/network analyzer, pattern-generator, etc.
working in front of various TEST teams, with the responsibility of addressing issues and monitoring the TEST flows conducted by them

the manager will be leading various type of reliability testings of nvidia ics, and responsible on nvidia reliability labs, which is a multi-millions $ worth of equipment as well as activities such as iqc, oqc, ic inventory managing and shipments.
this will include ate (automated TEST equipment), systems & evaluation boards and reliability equipment.
full management a team of technicians and operators, including day to day management, prioritization, focal reviews, and training.
maintaining and operating laboratory equipment such as ic ate, htol systems, scopes, dvms and other tooling, minimizing down time for all.
providing excellent support to engineers and our internal customers, carrying out q&r tasks and following strict execution methodologies.
establishing/maintaining a comprehensive engineering lab stock, apply skills to automate complex tasks and improve team productivity and efficiency.
entering and maintaining a database of work procedures and TEST data and reading schematics of electronic circuits.
building, updating, and improving lab processes and procedures while following and ensuring strict safety procedures and safety checks.

we are the production TEST team - responsible for the definition, development, and deployment of production TEST operations for the worlds most advanced socs for adas and self-driving vehicles.
this is your opportunity to join a team during its initial forming stage and leave your mark as our company assumes full ownership for its silicon production operations to enable high volume manufacturing for cutting-edge automotive products. what will your job look like?
work closely with the design teams from early stages of the design process to review dfx architecture and define TEST requirements.
define TEST methodologies and generate TEST content for high-speed interfaces of Embedded ip blocks (lpddr4/5, pcie gen4/5, d/ C /mphy).
TEST program coding, pattern conversion and pre-si validation (virtual TEST simulations)
support load board and probe card design activities.
lead post-si TEST program debug activities to enable delivery of samples to internal and external customers.
TEST program characterization and tuning to enhance TEST program quality to meet automotive standards.
support quality & reliability team to enable effective and timely qual plan execution.
lead TEST deployment activities with tier-one foundry and osat vendors to enable large-scale wafer-sort and final- TEST operations.

as a quality and reliability (q&r) engineer, you will lead the qualification and long-term reliability of advanced system -on-chip ( SOC ) and RF semiconductor products for automotive applications. youll work across digital and RF domains to ensure robust performance and compliance with industry standards. what will your job look like:
define and manage quality and reliability specifications, simulations, and qualification plans for SOC and RF die and package.
plan and execute automotive-grade qualifications per standards such as aec-q100, jedec jesd22, and iatf 16949.
design and implement die-level and package-level stress tests.
select and prepare electrical, environmental, and mechanical TEST platforms for reliability testing.
define requirements for pre-si q&r (e.g. esd, lu, em, ir drop), design-for- TEST (dft), electrical characterization, and post-si q&r testing of digital, mixed-signal and RF socs.
collaborate extensively with internal design teams, external subcontractors, and outsourcing partners (osats).
lead failure analysis, reliability modeling, and corrective action processes (e.g., 8d, fmea, fmeda).
document and certify automotive standards compliance, including ppap/apqp deliverables.

we are looking for a senior pcb design layout engineer to join our hardware engineering team at the autonomous vehicle platform department as a key player in the development of next-generation ecu (electrical control unit) for autonomous vehicles. what will your job look like?
working closely with hardware and mechanical design engineers, you'll perform pcb layout our ecus and other products.
complete development of cad layout from footprint definition, detailed component placement, constraints management, with a concept of topology and signal and power integrity.
be responsible for the design releases required generation of artwork files, odb++, fab drawings, ict report, and electronic pcb documentation.
your designs will need to follow ipc class 3, signal and power integrity constraints, emi/rfi control and automotive regulations.

architect end-to-end system validation strategies for new hardware platforms.
define TEST coverage and validation methodologies.
collaborate with hardware, software, qual and QA teams to align on product requirements and TEST coverage plans.
lead development of automation frameworks and diagnostics tools to enable scalable and repeatable testing.
analyze TEST data to identify root causes, guide debug efforts, and improve validation coverage.
provide technical leadership and mentorship across multidisciplinary teams and represent system TEST considerations in architecture and design reviews.

what you'll be doing:
support and develop solutions that will improve the efficiency and quality of the mixed-signal group.
define, develop, and maintain in-house, along with industrial utilities, solutions for schematic, layout, package and physical-verification in the fields of costume and eda vendor tools (cadence virtuoso, mentor calibre, synopsys icv and more), environment, and general-purpose solutions.
write, customize and debug icv/calibre runsets of drc, lvs, ext.
skill coding including pcells development.
scripting and programing for ad-hoc solutions and wide tasks solutions.
work closely with nvidias world-wide mixed-signal and technology teams.

we are now looking for best-in-class senior chip design Verification engineer to join our outstanding network adapter silicon group, developing the industry's best high-speed smart communication devices, data processing unit (dpu), delivering the highest throughput and lowest latency! come and take a significant part in verifying and designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a huge impact in a technology-focused company. 
what you'll be doing:
work in a verification team which develops some of the networking silicon core units.
build reference models, verify and simulate chip blocks/entities according to specifications under challenging constraints with high orientation to performance.
gain a strong understanding of chip micro-architecture and features, and develop the verification environments.
work closely with multiple teams within organizations such as architecture, micro- architecture, and fw.