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The System VnV team ensures our complex hardware-software products meet their intended requirements and function correctly before release. Our work plays a crucial role in ensuring quality assurance and mitigating risk with a strong focus on automation, data-driven insights, and cross-functional collaboration with development and hardware teams.

We are looking for a motivated and curious student to support our infrastructure and automation efforts. Youll help develop testing tools, integrate lab test equipment, and explore AI-based insights for smarter test analysis.

You'll be exposed to advanced lab setups, real-time testing systems, and tools that support product release decisions, all while being part of a high-performance engineering culture.

This is an ideal role for a student studying engineering or computer science, eager to gain real-world experience in system validation and automation.

Roles and responsibilities:
Design, develop, and maintain automated test infrastructure.
Develop tools to simulate, validate, and verify complex hardware/software systems.
Develop software interfaces to control and monitor test equipment (e.g., oscilloscopes, power supplies, signal generators, protocol analyzers).
Integrate AI/ML models for test optimization, log analysis, anomaly detection, root cause identification, and system insight.
Create dashboards, reports, and intelligent insights from test data and logs.

As a Senior Embedded Firmware Engineer, you will be the technical lead responsible for defining, implementing, and optimizing the embedded firmware that drives our ASIC. You will work closely with ASIC architects, hardware design teams, and software engineers to ensure a seamless and high-performance integration between silicon and system software.

Roles and responsibilities:
Own the HW/SW interface design for our Fully Homomorphic Encryption (FHE) ASIC, including low-level driver architecture.
Develop firmware from scratch, including boot code, device drivers, and control logic.
Collaborate with hardware and ASIC teams to define register maps, control protocols, and data paths.
Perform bring-up, debugging, and validation on prototype boards and silicon samples.
Optimize firmware for performance, reliability, and power efficiency.
Write technical documentation for firmware architecture, APIs, and hardware interface specifications.
Mentor junior engineers and contribute to best practices in embedded development.

Join a dynamic and innovative team driving the development of state-of-the-art EDA/CAD tools and scalable design automation infrastructure to empower advanced integrated circuit (IC) design. You will design, develop, and maintain next-generation design robust software tools and workflows across all domains in integrated circuit design, while ensuring compatibility with legacy software solutions.

Roles and responsibilities:
Design, develop, and maintain CAD/EDA tools and scalable software solutions to streamline workflows, improve design quality, and support all stages of the IC design lifecycle.
Lead CAD infrastructure operations, including tool debugging, flow refinement, continuous improvement, and seamless integration with design, verification, layout, and IT workflows.
Apply advanced CAD software engineering methods and research techniques to overcome technical challenges, assess architecture/hardware limitations, and define scalable solutions.
Architect and optimize Distributed Resource Management (DRM) tools in cloud environment, focusing on cost efficiency, scalability, and optimal resource utilization.
Establish and document best practices, standards, and procedures; provide technical analyses and recommendations; and deliver training and support to engineering teams.

We are looking for talented and ambitious individuals to join our Yoqneam IC team.

Roles and responsibilities:
The candidate will join our BE team, focusing on Full-Chip floor-planning, timing closure and integration, collaborating closely with frontend design, architecture, physical design, and analog teams. Additionally, the candidate will provide support to design teams across various methodologies and contribute to project execution efforts.
What will the candidate be doing
Lead Full Chip Layout activities & methodologies for a brand new SoC, from definition to Tape Out.
Floor Planning Top to Bottom & Bottom up FC, Sub System & Block level.
Involved in chip architecture, in close collaboration with the packaging, design & architecture teams. Exploring different floorplan structures to achieve both best area & ease of convergence.
Drive sign-off timing convergence for high performance designs at Full-chip and building block level.
Involved in definition of overall STA methodology, STA infrastructure and sign-off convergence flows, working closely with block owners throughout the project for sign-off timing convergence.
Work closely with EDA (Electronic Design Automation) vendors on latest tool feature development and qualification.