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We are looking for an experienced Firmware Engineer to join the NIC Firmware team at the Yokneam site. The Firmware team develops cutting edge networking features for cloud, HPC and storage. We drive the data growth of the worlds biggest companies. With talented engineers around the globe, the work environment is dynamic, meaningful, and fast-paced.
What you will be doing:
Work closely with the architecture and different software design teams.
Implement new features in the core of our company NIC firmware in pre and post silicon environment.
Develop verification tests for advanced features in a highly complex and sophisticated Firmware testing environment.
Gain a deep understanding of system debug, networking technology and stacks, as well as the HW/FW/SW relationship.
You will learn how a big software project is operated, maintained, qualified and released, and how Hardware and Firmware are developed.

Are you passionate about working on a team that is at the cutting and bleeding edge of hardware technology? Our Design-for-Test Engineering team at our company works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most sophisticated semiconductor chips. We are looking for an experienced DFT Engineer to join the SCAN INSERTION team. The position includes taking part in development of the next generation DFT technologies and working closely with a wide range of our groups and aspects - chip design, backend, verification, and production testing.
Working on the most advanced technologies and complex products, our DFT solution are unique and innovative internal developments, and we are continuously improving and evolving the solution to meet the challenging goals. If you find groundbreaking Technologies, and next generation products interesting, then this is the team for you. Take opportunity to join our team for an exciting and educational environment, where every individual has significant contribution to our products and achievements!
What youll be doing:
You will be in charge of state of the art Design for Test (SCAN INSERTION) flows and implementation
Take full SCAN INSERTION ownership end to end on a project, from Arch & planning to implementation and verification
Inventing and maintaining automation flows that provide SCAN INSERTION implementation to project .

we are looking for best-in-class Physical Design Manager to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
What you'll be doing:
Manage and Lead Physical Design team, up to 10 engineers.
Physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.
Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems.
Daily work involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
Taking part inflows development.

our company has been defining computer graphics, PC gaming, and accelerated computing for more than 25 years. With an outstanding legacy of innovation, driven by phenomenal technology, and extraordinary people, we are looking for a strong technical senior architect to join us in shaping the future. Senior Architects are innovators who can translate business needs into workable technology solutions. Their expertise is deep and broad. They are hands on, producing both detailed technical work and high-level architectural designs.
As a Senior architect in the Advanced Development team, you will explore technological challenges on accelerate networking and building AI data centers. Research new transport functions and semantics for optimizing AI workloads. You will also be leading architectural and development efforts across numerous technological fields, related to the modern data center, such as distributed AI and deep learning solutions, data analytics, High Performance Computing (HPC), Software Defined Networking (SDN), virtualization, storage, and more.
What youll be doing:
Enhance our company's GPU Networking offerings for accelerating AI workloads, such as our company Dynamo or our company NIXL.
Identify and evaluate new technologies, innovations and partner relationships for alignment with our technology roadmap and business value.
Lead architecture and design of such technologies.
Lead proof-of-concept development to evaluate and drive such technologies.

our company has been redefining computer graphics, PC gaming, and accelerated computing for more than 25 years. Its an outstanding legacy of innovation thats motivated by phenomenal technology. we are looking for a strong technical senior architect with the ability to craft architectural solutions, develop proof-of-concept code, and inspire engineering teams to achieve them. As a key member of our Advanced Development team, you'll drive emerging technologies in networking and distributed computing for the modern data center, such as distributed AI and Deep Learning solutions, Data Analytics, High Performance Computing (HPC), Software Defined Networking, Virtualization, Storage, and more.
What youll be doing:
Create proof-of-concept to evaluate and drive new technologies.
Work on impactful projects involving state-of-the-art high-performance computing software and hardware.
Research, design and develop hardware features relevant for scientific, Deep Learning, and data-intensive workloads.

we are seeking a sharp, innovative, and hands-on Architect to help shape the future of LLM inference at scale. Join our dynamic E2E Architecture group, where we build cutting-edge systems powering the next generation of generative AI workloads. In this role, you will work across software and hardware domains to design and optimize inference infrastructure for large language models running on some of the most advanced GPU clusters in the world.
Youll help define how AI models are deployed and scaled in production, driving decisions on everything from memory orchestration and compute scheduling to inter-node communication and system-level optimizations. This is an opportunity to work with top engineers, researchers, and partners across our company and leave a mark on the way generative AI reaches real-world applications.
What Youll Be Doing:
Design and evolve scalable architectures for multi-node LLM inference across GPU clusters.
Develop infrastructure to optimize latency, throughput, and cost-efficiency of serving large models in production.
Collaborate with model, systems, compiler, and networking teams to ensure holistic, high-performance solutions.
Prototype novel approaches to KV cache handling, tensor/pipeline parallel execution, and dynamic batching.
Evaluate and integrate new software and hardware technologies relevant to model inference (e.g., memory hierarchy, network topology, modern inference architectures).
Work closely with internal teams and external partners to translate high-level architecture into reliable, high-performance systems.
Author design documents, internal specs, and technical blog posts and contribute to open-source efforts when appropriate.

we are seeking best-in-class ASIC Verification Engineers to help deliver the worlds leading CPU's and SoC's. This position offers you the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. we are a learning machine that constantly evolves by adapting to new opportunities that are hard to pursue, that only we can take on, and that matter to the world. We have crafted a team of excellent people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.
we are building a new group in Israel, this group delivers security engines and risc-V processor IPs to all of our company's product lines working with all our company's groups around the world. We are looking for inquisitive, motivated engineers with experience to continue to build this new group. As a senior member of our team, you will be responsible for the verification of high-performance, low-power security engines and risc-V processor modules. You will work closely with architects, design engineers, FC verification engineers, and SW teams.
What you will be doing:
Participate in micro-architecture development and document specifications.
Build System Verilog UVM verification environments for IPs in areas of crypto and Risc-V platforms.
Build verification and test plans to get to complete coverage.
Work with the designers in our team to debug and clean all bugs
Deliver the IPs to higher level verification like Cluster, FC and emulation.

We are now looking for a Chip Design Verification Engineer. we are seeking a verification engineer to join the chip design methodologies team. The team is in charge of the verification methodologies, shared code, training, and embracing new technologies. One of our main goals is to make sure that the team works in an efficient manner, and provides high-quality deliveries. This position offers the opportunity to have real impact in a dynamic, technology-focused company.
What you'll be doing:
Develop shared verification code and solutions to be widely used by the chip design team.
Develop groundbreaking methodologies to create a flawless experience for verification engineers to keep the focus on new problems.
Collaborate with the design automation team to provide end-to-end solutions that combine verification, simulation, and automation.
Get in touch with EDA vendors to learn about cutting-edge tools/technology and apply them into our verification process.
Understand the design, define the verification scope, develop the verification infrastructure and verify the correctness of the design.
Collaborate with designers, verification specialists to accomplish your tasks.
Develop training sessions.

we are seeking an excellent Firmware Manager to join to GPU networking (NVLink) FW group in Tel-Aviv / Raanana. You will have the opportunity to lead development team responsible for the firmware of the next-generation networking products while being hands-on with development activities. We drive the data growth of the worlds biggest companies. With dedicated engineers around the globe, the work environment is dynamic, exciting, and fast-paced. Are you ready for the challenge?
What you will be doing:
Lead a team of engineers and provide technical guidance to the team of highly skilled engineers. Empower the team members to excel and increase team productivity.
Lead the design and implementation of new features in the core of our company GPU Networking firmware.
Drive and facilitate the planning, scheduling, and execution of the project and activities of the team
Collaborate with architecture and different software design teams as part of the software development lifecycle.
Work in pre and post-silicon development environments of next-generation our company GPU networking products.
Gain a deep understanding of networking technology, system debugging, and stacks, as well as the HW/FW/SW relationship.
Innovate! Bring our companys Networking products to shine in customers view.

we are at the forefront of AI-driven innovation in VLSI design automation. Join us to shape the future of semiconductor design with cutting-edge AI tools and make a significant impact in a collaborative, high-performance environment. Are you ready to push the boundaries of whats possible in VLSI CAD? Come be part of our pioneering team!
What you'll be doing:
You will be responsible for developing and integrating advanced CAD solutions and automation flows using AI and machine learning for VLSI design, verification, and implementation.
Work closely with design, verification, and CAD teams to identify areas for improving VLSI workflows using advanced tools and methods.
Research, prototype, and deploy AI-based algorithms.
Develop and maintain scripts and automation infrastructure to enable seamless adoption of AI tools in the VLSI design process.
Continuously review emerging AI technologies and methodologies to keep our CAD environment up-to-date.
Provide technical support and training to engineering teams on AI-enabled CAD flows and best practices.

Are you passionate about working on a team that is at the cutting and bleeding edge of hardware technology? Our Design-for-Test Engineering team at our company works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most sophisticated semiconductor chips. We are looking for an experienced DFT Engineer to join the ATPG team. The position includes taking part in development of the next generation DFT technologies and working closely with a wide range of our groups and aspects - chip design, backend, verification, and production testing.
Working on the most advanced technologies and complex products, our DFT solution are unique and innovative internal developments, and we are continuously improving and evolving the solution to meet the challenging goals. If you find groundbreaking Technologies, and next generation products interesting, then this is the team for you. Take opportunity to join our team for an exciting and educational environment, where every individual has significant contribution to our products and achievements!
What youll be doing:
You will be in charge of state of the art Design for Test/ATPG flows and implementation
Take full ATPG ownership end to end on a project, from Arch & planning to pattern generation, verification and post Silicon bring up and diagnosis.
Inventing and maintaining automation flows that provide the short test time to production.

we are seeking a highly motivated and experienced System Test Architect to define, develop, and drive comprehensive validation strategies for next-generation hardware platforms. As a key member of our hardware architecture and systems engineering team, you will be responsible for ensuring the robustness, performance, and scalability of our company's cutting-edge products across AI, graphics, data center, and automotive domains. You will collaborate with cross-functional teamsincluding silicon design, board design, firmware, and software engineeringto create innovative test methodologies that validate complex system-level interactions. Your insights and expertise will directly impact product quality, development efficiency, and time-to-market.
What you will be doing:
Architect end-to-end system validation strategies for new hardware platforms.
Define test coverage and validation methodologies.
Collaborate with hardware, software, Qual and QA teams to align on product requirements and test coverage plans.
Lead development of automation frameworks and diagnostics tools to enable scalable and repeatable testing.
Analyze test data to identify root causes, guide debug efforts, and improve validation coverage.
Provide technical leadership and mentorship across multidisciplinary teams and represent system test considerations in architecture and design reviews.

We are now looking for best-in-class Senior Chip Design Verification Engineer to join our outstanding Network Adapter Silicon group, developing the industry's best high-speed smart communication devices, Data Processing Unit (DPU), delivering the highest throughput and lowest latency! Come and take a significant part in verifying and designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a huge impact in a technology-focused company.
What you'll be doing:
Work within a Networking Fullchip team, which is responsible for delivering the chip to tapeout and serves as a critical verification stage before final chip release.
Gain a strong understanding of chip micro-architecture and features, and develop the verification strategyincluding checkers, testcases, and debug plans - for fullchip/cluster level validation.
Enable and validate new features at the fullchip/cluster level, ensuring high quality and reliability under challenging constraints.
Be an integral part of an innovative team, actively participating in the creation and implementation of new verification infrastructures using advanced AI tools.