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our company has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It's an outstanding legacy of innovation that's fueled by great technologyand outstanding people. Today, were tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing whats never been done before takes vision, innovation, and the worlds best talent. As an worker, youll be immersed in a diverse, encouraging environment where everyone is motivated to do their best work. Come join the team and see how you can make a lasting impact on the world.
We are seeking an experienced Malware Research Architect who can design and implement advanced malware detection systems using Virtual Machine Introspection (VMI) techniques. The ideal candidate should have deep expertise in developing out-of-VM security solutions that can detect and analyze sophisticated malware, rootkits, and other cyber threats by introspecting and reconstructing volatile memory states of guest operating systems and file system states. Strong knowledge of file systems, and hypervisor technologies is essential. The candidate will craft automated malware detection systems that use VMI and file system techniques to predict early signs of malware execution and accurately classify unknown threats.
What you'll be doing:
Lead, research, design, develop and implement solutions for next-generation secure networks.
Develop novel introspection, memory forensics, and file system methods to extract critical security events towards threat detection.
Collaborate with external and internal hardware and software research teams to apply extracted events for advanced malware detection.
Architectural modeling, validation, microarchitectural definition, and developing proof-of-concepts secure platforms.

we are looking for a best-in-class STA Engineer to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking large scale and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
What you will be doing:
Be in charge of full-chip/Chiplet level STA convergence from early stages to signoff.
Take part in floor plan design and Netlist creation with aim to optimize timing convergence and work efficiency.
Define and optimize, together with CAD, STA signoff flows and methodologies.
Digital Partitions' and analog IPs' timing integration, giving feedback and driving convergence.
Work closely with logic design and DFT engineers to define and implement constraints for the various work modes, including optimizing them for runtime and efficiency.

We are looking for a Senior Chip Design Engineer, Formal Verification for our company's Networking team!
This is an exciting opportunity to join a hardworking Pre-Silicon design and verification team, working on groundbreaking Switch and GPU technologies. We deploy state-of-the art formal verification tools and methodologies to prove design correctness. Working in our formal verification team will expose you to a wide range of cutting edge design and technologies that are in the heart of the AI revolution. Our team delivers world class Chips solutions for HPC, AI infrastructures, data-center, network, and storage markets. We micro-architect, verify, and deliver smart and high bandwidth multi port switches. our company has the most sophisticated formal tools and methodologies in the industry, which help us achieve A0 design tape-outs. As part of this team, you'll enjoy a versatile work environment, which is educational, dynamic and ambitious.
What you'll be doing:
In this position you will use formal verification algorithms to formally prove the correctness of complicated logic problems.
You will work on ambitious designs along with our Pre-Silicon team and take part in developing the next generation of our company's core technology.
You will take part in the AI revolution led by our company, working on cutting edge architecture.

our companys CTO Group is looking for experienced Algorithm Researchers and Developers to join our team! Which department will you join? The CTO Group is a small, elite group, whose goal is to build next-generation algorithmic solutions powering our companys self-driving car, crowd-sourced HD maps, and advanced driver-assistance systems. The group is primarily focused on the decision-making module of our company's self-driving car. It leverages a wide range of algorithmic approaches, rigorous formal definitions, and mathematical modeling- enriched by insights drawn from large-scale data and real-world driving experience. The group is comprised of top-notch developers and researchers and is headed by world-class scientists. This is a unique opportunity for a passionate technical leader to join the CTO Group, work closely with the CTO on next-generation projects, develop POCs using cutting-edge technologies, shape our technology vision and provide thought leadership to our technical community.
What will your job look like:
Research, design and develop innovative algorithmic solutions.
Mathematical modeling and abstraction of real-life problems.
Code design, implementation, and hands-on development.

our companys CTO Group is looking for experienced Algorithm Researchers and Developers to join our team! Which department will you join? The CTO Group is a small, elite group, whose goal is to build next-generation algorithmic solutions powering our companys self-driving car, crowd-sourced HD maps, and advanced driver-assistance systems. The group is primarily focused on the decision-making module of our company's self-driving car. It leverages a wide range of algorithmic approaches, rigorous formal definitions, and mathematical modeling- enriched by insights drawn from large-scale data and real-world driving experience. The group is comprised of top-notch developers and researchers and is headed by world-class scientists. This is a unique opportunity for a passionate technical leader to join the CTO Group, work closely with the CTO on next-generation projects, develop POCs using cutting-edge technologies, shape our technology vision and provide thought leadership to our technical community.
What will your job look like:
Research, design and develop innovative algorithmic solutions.
Mathematical modeling and abstraction of real-life problems.
Code design, implementation, and hands-on development.

Which department will you join? our company's VLSI team - a group designing the EyeQ chips for ADAS and autonomous cars. The group is responsible for all disciplines of VLSI development, including but not limited to Logic Design, Design Verification, Microarchitecture, Analog and circuit design and layout, Physical and structural design (backend), Product and test engineering. Each Physical Design engineer has an end to end responsibility from definition, execution & full signoffs, working closely with design & architecture teams for constraints development, design review & RTL modifications to achieve converges Were looking for a Backend Engineer to join the growing Physical Design Team, responsible for state of the art SoC design from definition to Tape-Out.
What will your job look like:
Hands-on physical design block owner from RTL to GDS.
Floorplan exploration with guidance and collaboration with front-end and architecture teams.
STA: work with FE and floor planner to manage block and top level constraints and 1st level of timing analysis.
Synthesis exploration and final synthesis netlist: Scan insertion @ synthesis, clean checks from Lint, UPF & Spyglass.
Place & Route: from Synthesis netlist to final layout and signoff verification with target to achieve best power performance and area.

we are looking for a Embedded SW Engineer for Performance Modeling. You will be part of EyeQ SoC Performance Modeling and Profiling team in EyeQ Platform Group (EPG), working on current and next-generation designs for ADAS/AV. Performance models and profiling tools are fundamental parts of the EPG infrastructure, they are used during EyeQ HW architecture definition phase and by SW developers for performance optimizations.
What will your job look like:
You will work on CPU functional and timing models of our company's SoC platforms.
You will work on developing tracing and profiling tools for CPU performance analysis and optimizations.
You will run HW benchmarks to test HW performance and calibrate the simulation performance with the silicon board.
You will have the opportunity to work on open-source simulation and profiling tools and adopt them to our company's needs.
You will work closely with HW architects and SW/OS/Algorithms developers.

The company's EyeC VLSI team specializes in designing advanced radar system chips for ADAS (Advanced Driver Assistance Systems) and autonomous vehicles. The group is responsible for all disciplines of VLSI development, including but not limited to Logic Design, Design Verification, Microarchitecture, Analog and circuit design and layout, Physical and structural design (backend), Product and test engineering.
What will your job look like:
Design ownership on major blocks/clusters from definition to implementation phase.
Participate in various ASIC activities and flow definition which includes CDC, DFT, Lint.
Design micro-architecture of custom blocks.

The company's EyeC VLSI team specializes in designing advanced radar system chips for ADAS (Advanced Driver Assistance Systems) and autonomous vehicles. The group is responsible for all disciplines of VLSI development, including but not limited to Logic Design, Design Verification, Microarchitecture, Analog and circuit design and layout, Physical and structural design (backend), Product and test engineering.
What will your job look like:
Design ownership on major blocks/clusters from definition to implementation phase.
Participate in various ASIC activities and flow definition which includes CDC, DFT, Lint.
Design micro-architecture of custom blocks.

The company's EyeC VLSI team designs chips for RADAR systems used in ADAS and autonomous vehicles. Our Physical Design team operates in a startup-like environment, emphasizing technical expertise, execution, and ownership. Each engineer in the Physical Design team takes full responsibility for their work, from initial definition through execution and final sign-offs. Engineers collaborate closely with design and architecture teams to develop constraints, conduct design reviews, and implement RTL modifications to ensure convergence. We are seeking an Experienced Backend to join our growing Physical Design team. In this role, you will play a key part in the design of state-of-the-art SoCs, from definition to Tape-Out.
What will your job look like:
Hands-on physical design block owner from RTL to GDS.
Floorplan exploration with guidance and collaboration with front-end and architecture teams.
STA: work with FE and floor planner to manage block and top level constraints and 1st level of timing analysis.
Synthesis exploration and final synthesis netlist: Scan insertion @ synthesis, clean checks from Lint, UPF & Spyglass.
Place & Route: from Synthesis netlist to final layout and signoff verification with target to achieve best power performance and area.
Signoff : on all physical design domains- STA, IR/EM, Physical Verification, Logic Equivalent Checking, Low Power Verification.

our company's EyeC VLSI team - a group designing the chips for RADAR systems for ADAS and autonomous cars. Our Physical Design group is working in a Startup like environment with respect to technical expertise, execution & responsibility . Each Physical Design engineer has an end to end responsibility from definition, execution & full signoffs, working closely with design & architecture teams for constraints development, design review & RTL modifications to achieve converges Were looking for a Experienced Physical Design Engineer to join the growing Physical Design Team, responsible for developing our next generation Imagining Radar SoC from definition to Tape-Out.
What will your job look like:
Hands-on physical design block owner from RTL to GDS with horizontal ownership.
Floorplan exploration and collaboration with front-end and architecture teams.
Synthesis exploration and final synthesis including: SDC definition, Scan insertion, Lint, LEC, UPF-LP & Spyglass verification.
Place & Route: from Synthesis to final layout and signoff verification on all tools and floors, with target to achieve best PPA.
STA: timing analysis, working with Sub System and Full Chip owners to manage block and top level constraints for synthesis, P&R and signoff.

The RFIC/Analog design groups in our company's Radar organization is responsible for developing the cutting edge Transceivers in mmW frequencies for the best Imaging Radar technology. The design process includes the entire process from specs to productization. To support these challenging processes, we need a skilled CAD team that will work with the design teams on all design aspects and flows from design environment setups, through design tools implementations and support and to chip level verifications and validation enablement. We're looking for an Experienced CAD or Design Automation Engineer to develop our company's RF/Analog design tools/flows and automation flows for the next-generation Imaging Radar chips.
What will your job look like:
Build and support RF/analog design environments
Implement, develop, and maintain design flows, tools and scripts.
Evaluate and explore new automation technologies and advocate for efficiency improvements
Evaluate multiple vendor solutions and guide execution, in the most optimal use, based on design needs
Effectively communicate and support a large number of designers, providing high-quality tools and flows, documentation, and presentations.

The RFIC/Analog design groups in our company's Radar organization is responsible for developing the cutting edge Transceivers in mmW frequencies for the best Imaging Radar technology. The design process includes the entire process from specs to productization. To support these challenging processes, we need a skilled CAD team that will work with the design teams on all design aspects and flows from design environment setups, through design tools implementations and support and to chip level verifications and validation enablement. We're looking for an Experienced CAD or Design Automation Engineer to develop our company's RF/Analog design tools/flows and automation flows for the next-generation Imaging Radar chips.
What will your job look like:
Build and support RF/analog design environments
Implement, develop, and maintain design flows, tools and scripts.
Evaluate and explore new automation technologies and advocate for efficiency improvements
Evaluate multiple vendor solutions and guide execution, in the most optimal use, based on design needs
Effectively communicate and support a large number of designers, providing high-quality tools and flows, documentation, and presentations.

our company's Automated Driving group in Haifa is looking for an experienced SoC Design Engineer for DFT team. This is an exciting opportunity to join a team of highly talented engineers, working on one of the most cutting edge technologies - Autonomous Vehicle (AV) SoC. At our company's Automated Driving group, we know that the idea of a fully autonomous car is no longer science fiction, but a reality that we are creating! We have spent more than 15 years developing the world's most Advanced Driver Assistance Systems (ADAS) and we are now leading the computer vision and machine learning domain, reaching fully automated driving experience (AV).
What will your job look like:
You'll be responsible of architecture of the DFT solutions across the SOC (MBIST, SCAN, ATPG, LBIST and more)
Develop all the necessary HW / FW / SW for the different modules
Verify and Validate our design
Debug and analyze coverage and yield loss
As a cutting edge technology company, we are working only with the very advanced DFT tools and features, while developing our own methods and DFT concepts as it required by the Automotive and Safety related products market (ISO26262).

Which team will you join? our company EyeC VLSI team - a group designing the chips for Radar systems for ADAS and autonomous cars. The group is responsible for all disciplines of VLSI development, including but not limited to Logic Design, Design Verification, Microarchitecture, Analog and circuit design and layout, Physical and structural design (backend), Product and test engineering.
What will your job look like:
You will take a central hands-on role in Design Verification.
Define Environment micro-Architect, Implement complex UVM environment, Build vPlan .
Execute coverage implementation.
Be part of external IP verification and Internal custom IP.
Be part of System definition and top-level activity.
Take part in Silicon bring-up.