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Requied Full Chip CAD Physical Design Engineer
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.The AI and Infrastructure team is redefining whats possible.
We're the driving force behind our groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Cloud, Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Demonstrate an understanding of the Register-Transfer Level (RTL) to Graphic Data Stream (GDS) II flow.
Manage the implementation of large, complex system-on-chips (SoCs), subsystems, and sub-wrappers, and demonstrate an understanding of associated issues and solutions.
Utilize floorplanning, power grid design, and place-and-route methodologies, and use Synopsys tools like Floorplan Compiler (FC) and Formality.
Exhibit an understanding of advanced node design (e.g., 5nm and below) and related optimization techniques.
Develop script in Synopsys TCL and Python.

Required Senior SoC Formal Verification Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Our mission is to build the best cloud in the world for our services and for our Cloud customers, by solving real world business issues of performance, cost, and scale, utilizing hardware, software, and system solutions. To better serve evolving cloud needs, we are establishing a team in Israel to develop custom chips for servers.
In this role, you will perform formal verification of design properties of complex ASIC designs. You will collaborate closely with design and verification engineers to define meaningful properties that capture the design intent of a logic block and constraints on its input stimulus. You will also help define and improve design and verification methodologies that allow you to achieve formal verification closure.
Our mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
Plan the formal verification strategy and create the properties and constraints for complex digital design blocks.
Utilize formal property verification tools combined with formal verification closure techniques to verify properties and apply sign-off to blocks.
Pioneer and refine formal verification methodologies by systematically embedding AI tools to optimize verification accuracy.
Architect and implement reusable formal verification components.

Required Technical Program Manager, Silicon Design Services and Strategic Extended Workforce
About the job
A problem isnt truly solved until its solved for all. Thats why we build products that help create opportunities for everyone, whether down the street or across the globe. As a Technical Program Manager, youll use your technical expertise to lead complex, multi-disciplinary projects from start to finish. Youll work with stakeholders to plan requirements, identify risks, manage project schedules, and communicate clearly with cross-functional partners across the company. You're equally comfortable explaining your team's analyses and recommendations to executives as you are discussing the technical tradeoffs in product development with engineers.
Behind all of our user-facing AI models, applications, and cloud services is an advanced data center infrastructure powered by custom silicon designed by us.
As the Lead Technical Program Manager for Silicon Design Services and Strategic Extended Workforce, you will drive the end-to-end technical engagement, program management, and operational execution of our multi-vendor design services ecosystem. You will lead cross-functional programs spanning external partner selection (RFI/RFP), technical scoping, Statement of Work (SOW) drafting, and day-to-day execution across multiple development functions such as: Physical Design, Design for Test, Verification, and Silicon Engineering (SiEng/NPI). You will serve as the critical technical bridge between our internal silicon design/architecture teams and external design partners, ensuring execution velocity, first-pass silicon quality, IP security, and commercial alignment.
Responsibilities
Lead end-to-end program lifecycles for external design services from scoping, RFP, and SOW finalization through tapeout and production ramp.
Establish multi-tiered vendor governance frameworks and drive critical technical, budgetary, and schedule tradeoff discussions between internal and external leadership.
Partner with our execution owners and vendors to align milestone deliverables, sign-off criteria, and dependency tracking for advanced node SoCs.
Deploy secure Cloud CAD development environments and manage outsourced silicon NPI, including ATE test development and OSAT manufacturing handoffs.
Define Key Performance Indicators (KPIs) and Service-Level Agreements (SLAs) to track milestone adherence, pro-actively mitigate critical-path program risks, and govern strategic commercial agreement terms.

Required Senior Silicon DFT Lead
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As the Design for Test (DFT) Engineer Lead, you will play a crucial role in DFT Architecture and DFT design, and support devices to production. You will be responsible for providing technical leadership in DFT, developing flows, automation, and methodology, planning DFT activities, tracking the DFT quality throughout the project life-cycle, and providing sign-off DFT to tapeout.
Responsibilities
Lead and execute DFT activities in the design, implementation, and verification solutions for Application-Specific Integrated Circuits (ASIC).
Develop DFT strategy and architecture, including hierarchical DFT, Memory Built-In Self Test (MBIST), and Automatic Test Pattern Generation (ATPG).
Work with other Engineering teams (e.g., Design, Verification, Physical Design) to ensure that DFT requirements are met and mutual dependencies are managed.
Manage a DFT team planning, deliverables, and provide technical mentoring and guidance.
Lead DFT execution of a silicon project, planning, execution, tracking, quality, and signoff.

Required CPU Design for Test Engineer, Cloud
About the job
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of our platforms, we make our product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
In this role, you will be part of a varied team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You will contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next-generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a Design-for-Test (DFT) Engineer, you will play a crucial role in DFT design, and support devices of extreme complexity to production. You will be responsible for developing flows, automation, and methodology, executing DFT activities. You will be responsible for test vectors end-to-end, from generating DFT content on complex design, debugging to coverage goals, simulating it at gate level, sign-off DFT to tapeout, and debugging Si results.
Responsibilities:
Execute activities in the design, implementation, and verification of Design for Testing solutions for Application-Specific Integrated Circuit (ASICs).
Develop DFT strategy for array DFT, hierarchical DFT, Scan, and Automatic Test Pattern Generation (ATPG).
Perform ATPG, scan coverage debug and drive design fixes for coverage and quality improvements.
Perform DFT verification at RTL and gate level.
Work with other Engineering teams (e.g., Design, Verification, Physical Design) to ensure that DFT design requirements are met and mutual dependencies are managed.

Our company is seeking a Hardware Development Team Lead to lead cross-functional development and integration activities across the organization. The successful candidate will oversee collaboration between all engineering disciplines, including Hardware, RF, Software, and Firmware, while serving as the key interface with the Systems Engineering team.
Key Responsibilities:
Lead and directly manage a multidisciplinary engineering team developing complex systems, including Mechanical, Hardware, Firmware, and RF engineers, ensuring execution according to project plans, schedules, and objectives.
Lead end-to-end product development, including system architecture definition, technical oversight, prototype development, and design verification and validation (V&V).
Serve as the primary liaison between development engineers, the Systems Engineering team, and Project Managers.
Evaluate, introduce, and implement new development tools, methodologies, and emerging technologies.
Define priorities and allocate engineering tasks based on business needs, project requirements, and market considerations.
Establish engineering methodologies, development processes, project milestones, and required deliverables for internal design reviews (PDR, CDR, etc.).
Define engineering roles and responsibilities, recruit new team members, mentor engineers, conduct performance evaluations, and develop individualized professional growth plans.
Conduct routine management activities, including status meetings, management reviews, and project progress meetings.
Prepare technical responses for project tenders (RFPs), including technical proposals, effort estimation, and cost evaluation.
Provide technical support for both internal engineering challenges and customer-facing technical issues.
Lead internal and customer design reviews as required.

we are looking for a talented Hardware Board Designer to join our multidisciplinary R&D team. This is an exciting opportunity to take part in the design and development of advanced electronic systems, working alongside hardware, firmware, software, and system engineers from concept through integration.
We are looking for a creative, hands-on engineer with a passion for hardware design and a desire to work on cutting-edge technologies.
Responsibilities
Design and develop complex electronic boards from concept to production.
Perform hands-on schematic design and component selection.
Support and guide PCB layout activities.
Prepare and present design reviews.
Collaborate closely with firmware, software, RF, and system engineering teams to ensure successful system integration.
Develop advanced multidisciplinary systems incorporating:
CPUs / SoCs
FPGA-based designs
Analog and mixed-signal circuits
High-speed interfaces (DDR, PCIe, Ethernet, LVDS, etc.)
RF transmit and receive chains
Filters and amplifier circuits
Power supply and power management circuits
Support board bring-up, debugging, validation, and troubleshooting.

Required Senior Silicon Physical Design Engineer
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a SoC Physical Design Engineer, you will collaborate with functional design, Design for Testing (DFT), architecture, and packaging engineers. In this role, you will solve technical problems with innovative micro-architecture and practical logic circuits solutions, while evaluating design options with optimized performance, power, and area in mind.
Responsibilities
Use problem-solving and simulation techniques to ensure performance, power, and area (PPA) are within defined requirements.
Collaborate with cross-functional teams to debug failures or performance shortfalls and meet program goals in lab or simulation.
Design chips, chip-subsystems, or partitions within subsystems from synthesis through place and route, and sign off convergence, ensuring that the design meets the architecture goals of power, performance, and area.
Develop, validate, and improve Electronic Design Automation (EDA) methodology for a specialized sign off or implementation domain to enable cross-functional teams to build and deliver blocks that are correct by construction and ease convergence efforts.

Required Signal/Power Integrity Engineer, PhD Graduate
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Responsibilities:
Simulate high speed interface electrical behavior using HSPICE or other circuit simulators.
Generate precise electrical models (e.g., S-parameters, SPICE models) for components such as packages, PCBs, and connectors for use in simulations.
Collaborate extensively with cross-functional teams, including ASIC architects, digital/analog designers, physical design/layout engineers, and system engineers, to define specifications and resolve integration challenges.
Execute lab measurements utilizing test equipment like oscilloscopes, Vector Network Analyzers (VNA), Time Domain Reflectometers (TDR) , Spectrum analyzers to validate simulation outcomes and debug signal and power-related issues on silicon prototypes and boards.
Establish robust design rules and guidelines for optimal signal/power integrity during PCB and package layout, ensuring high production yield and reliability.

Required Networking Silicon Architect, Cloud
About the job
In this role, youll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers our most demanding AI/ML applications. Youll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
As a part of the team, you will define solutions for high-performance network accelerators and interconnects in data centers. You will have dynamic, multi-faceted responsibilities in areas such as project definition, with close collaborations with data center systems and Software teams. You will participate in the design, architecture, documentation, and implementation of the next generation of data center networking infrastructure.
You will be responsible for performance analysis for an end-to-end networking stack using your deep knowledge of high speed network infrastructure.
We're behind groundbreaking innovations, empowering the development of AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Cloud, Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Evaluate different silicon solutions for executing our data center networking roadmap, off-the-shelf components, vendor co-developments, custom designs, and advanced silicon integration technologies.
Design high-performance hardware/software interfaces.
Collaborate closely with system, software, verification, emulation, physical design, packaging, and silicon validation stakeholders to ensure that designs are complete, correct, and performant.
Drive vendor execution in various engagements: standard component roadmaps, build to specification, and co-developments.
Contribute to the evaluation of future ASIC designs and general architecture.

Required RTL Design Technical Lead, Servers, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As part of our Server Chip Design team, you will use the ASIC design experience to be part of a team that creates the SoC VLSI design cycle from start to finish. You will collaborate with design and verification engineers in active projects, creating architecture definitions with RTL coding, and running block level simulations.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Lead the Design Activities at IPs, SubSystems(S.S) and SoC.
Plan, execute, track progress, assure quality, report status of the assigned activity.
Lead a team of designers both directly and in teams.
Define the Block/SoC level design documents such as Micro Architectural Specifications.
Own IP, S, SoC strategies for clocks, resets, and debugs. Enforce global methodologies and drive enhancements.

we are a global pioneer of RADAR systems for active military protection, counter-drone applications, critical infrastructure protection, and border surveillance. We are looking for a motivated and experienced Supply Chain Master data Specialist to join our team! The data Master is responsible for the governance, accuracy, and maintenance of core business data across ERP systems, including Oracle Cloud ERP where applicable. The role ensures high-quality master data to support seamless business operations and reliable transactional processing across Supply Chain, Operations, Finance, and customer-related processes. The position is part of the Supply Chain organization and has matrix alignment with IT/MIS and Finance for data governance, ERP processes, and system alignment. Key Responsibilities 1. Master data Management:
* Maintain and update core master data entities, including Items, suppliers, BOMs/product structures, price lists, accounts, and customer-related data.
* Ensure data accuracy, completeness, and consistency across ERP systems, and support ongoing data cleansing and standardization initiatives. 2. data Governance & Quality Control:
* Define and enforce data governance policies, standards, naming conventions, validation rules, and approval workflows.
* Monitor data quality, including duplicates, completeness, and consistency, and support data ownership and control processes across business functions. 3. Cross-Functional Coordination:
* Serve as the focal point between Supply Chain, Finance, and IT/MIS for data -related topics.
* Support business users in data setup and issue resolution, and align data structures with ERP best practices while minimizing unnecessary customization. 4. ERP Implementation & Migration Support:
* Support ERP implementation and enhancement projects, including data extraction, cleansing, transformation, loading, validation, and UAT.
* Ensure migrated and new data is ready to support business operations before deployment. 5. Operational Support:
* Ensure timely data availability to support orders, procurement, planning, production, inventory, customer, and finance-related transactions.
* Troubleshoot master data issues impacting business processes and continuously improve data processes and automation opportunities. Key Interfaces:
* Material Management, Planning & MRP, Procurement, Warehousing & Inventory Control, Manufacturing & Factory Operations, Engineering and Quality, Finance, IT/MIS, External vendors and ERP implementation partners

Required Senior CAD Infra Engineer
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.our mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
Work with partner teams to provide the compute, storage, and methodology needs of the chip design, verification, and physical design teams. Collaborate with Application-Specific Integrated Circuit (ASIC) teams to implement tools and methodologies.
Design and implement CAD tools, solutions, and methodologies for ASIC development. Extend the capabilities of third-party tools through their dedicated APIs.
Propose, design, and implement software automation that directly addresses bottlenecks in today's ASIC and SoC EDA flow. Lead and actively contribute to the automation and integration of physical design (floorplanning, power planning, synthesis, place and route, clock tree synthesis, timing closure, STA, DRC, LVS, DFM, etc.) in our automated flow.
Leverage your software expertise to develop the hardware automations required for physical design automation, and their software integration in our automated flow.